82583V Datasheet, PDF (243/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Note:
9.2.5.19
These registers contain the lower bits of the 48-bit Ethernet address. All 32 bits are
valid.
If the NVM is present the first register (RAL0) is loaded from the NVM.
These registers' addresses have been moved from where they were located in previous
devices. However, for backwards compatibility, these registers can also be accessed at
their alias offsets of 0x0040-0x000BC.
Receive Address High - RAH (0x05404 + 8*n; RW)
While "n" is the exact unicast/Multicast address entry and it is equals to 0,1,…15
Note:
Note:
Note:
Field
RAH
ASEL
Reserved
AV
Bit(s)
15:0
17:16
30:18
31
Initial
Value
X
X
0x0
X
Description
Receive Address High
The upper 16 bits of the 48-bit Ethernet address.
Address Select
Selects how the address is to be used. Decoded as follows:
00b = Destination address (must be set to this in normal mode).
01b = Source address.
10b = Reserved.
11b = Reserved.
Reserved
Reads as 0x0. Ignored on write.
Address Valid
Cleared after master reset. If the NVM is present, the Address Valid
field of Receive Address Register 0 are set to 1b after a software or
PCI reset or NVM read.
In entries 0-14 this bit is cleared by master reset. The AV bit of entry
15 is cleared by Internal Power On Reset.
These registers contain the upper bits of the 48-bit Ethernet address. The complete
address is {RAH, RAL}. AV determines whether this address is compared against the
incoming packet. AV is cleared by a master reset in entries 0-14, and on Internal Power
On Reset in entry 15.
ASEL enables the device to perform special filtering on receive packets.
The first receive address register (RAR0) is also used for exact match pause frame
checking (DA matches the first register). Therefore RAR0 should always be used to
store the individual Ethernet MAC address of the 82583V.
These registers' addresses have been moved from where they were located in previous
devices. However, for backwards compatibility, these registers can also be accessed at
their alias offsets of 0x0040-0x000BC.
After reset, if the NVM is present, the first register (Receive Address Register 0) is
loaded from the IA field in the NVM, its Address Select field will be 00b, and its Address
Valid field will be 1b. If no NVM is present the Address Valid field for n=0b will be 0b.
The Address Valid field for all of the other registers is 0b.
The software device driver can use only entries 0-14.
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