82583V Datasheet, PDF (53/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Initialization—82583V GbE Controller
Note:
4.6.4
• MAC duplex and speed settings forced by software based on resolution of
PHY. (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.ASDE = don't care)
— CTRL.FD - Set by software based on reading PHY status register after the PHY
has auto-negotiated a successful link-up.
— CTRL.SLU. - Must be set to 1b by software to enable communications between
the MAC and PHY.
— CTRL.RFCE - Must be set by software after reading flow control resolution from
the PHY registers.
— CTRL.TFCE - Must be set by software after reading flow control resolution from
the PHY registers.
— CTRL.SPEED - Set by software based on reading PHY status register after the
PHY has auto-negotiated a successful link-up.
— STATUS.FD - Reflects the MAC forced duplex setting written to CTRL.FD.
— STATUS.LU - Reflects link indication (LINK) from the PHY qualified with
CTRL.SLU (set to 1b).
— STATUS.SPEED - Reflects MAC forced speed setting written in CTRL.SPEED.
• MAC/PHY duplex and speed settings both forced by software (fully-forced
link setup). (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.SLU = 1b)
— CTRL.FD - Set by software to desired full-/half- duplex operation (must match
duplex setting of the PHY).
— CTRL.SLU - Must be set to 1b by software to enable communications between
the MAC and PHY. The PHY must also be forced/configured to indicate positive
link indication (LINK) to the MAC.
— CTRL.RFCE - Must be set by software to the desired flow-control operation
(must match flow-control settings of the PHY).
— CTRL.TFCE - Must be set by software to the desired flow-control operation
(must match flow-control settings of the PHY).
— CTRL.SPEED - Set by software to desired link speed (must match speed setting
of the PHY).
— STATUS.FD - Reflects the MAC duplex setting written by software to CTRL.FD.
— STATUS.LU - Reflects 1b (positive link indication LINK from PHY qualified with
CTRL.SLU).
Since both CTRL.SLU and the PHY link indication LINK are forced, this bit set does not
guarantee that operation of the link has been truly established.
— STATUS.SPEED - Reflects MAC forced speed setting written in CTRL.SPEED.
Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular
register's description. The initialization of these registers begins at transition to D0
active power state (when internal registers become accessible, as enabled by setting
the Memory Access Enable field of the PCIe Command register), and is guaranteed to
complete within 1 ms of this transition. Access to statistics registers prior to this
interval might return indeterminate values.
All of the statistical counters are cleared on read and a typical software device driver
reads them (thus making them zero) as a part of the initialization sequence.
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