82583V Datasheet, PDF (253/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.7.1
CRC Error Count - CRCERRS (0x04000; R)
9.2.7.2
Field
CEC
Bit(s)
31:0
Initial
Value
0x0
CRC Error Count
Description
Counts the number of receive packets with CRC errors. In order for a packet to be
counted in this register, it must pass address filtering and must be 64 bytes or greater
(from <Destination Address> through <CRC>, inclusively) in length. If receives are not
enabled, then this register does not increment.
Alignment Error Count - ALGNERRC (0x04004; R)
9.2.7.3
Field
AEC
Bit(s)
31:0
Initial
Value
0x0
Alignment Error Count
Description
Counts the number of receive packets with alignment errors (such as the packet is not
an integer number of bytes in length). In order for a packet to be counted in this
register, it must pass address filtering and must be 64 bytes or greater (from
<Destination Address> through <CRC>, inclusively) in length. If receives are not
enabled, then this register does not increment. This register is valid only in MII mode
during 10/100 Mb/s operation.
RX Error Count - RXERRC (0x0400C; R)
9.2.7.4
Field
RXEC
Bit(s)
31:0
Initial
Value
0x0
RX Error Count
Description
Counts the number of packets received in which RX_ER was asserted by the PHY. In
order for a packet to be counted in this register, it must pass address filtering and must
be 64 bytes or greater (from <Destination Address> through <CRC>, inclusively) in
length. If receives are not enabled, then this register does not increment.
Missed Packets Count - MPC (0x04010; R)
Note:
Field
MPC
Bit(s)
31:0
Initial
Value
0x0
Missed Packets Count
Description
Counts the number of missed packets. Packets are missed when the receive FIFO has
insufficient space to store the incoming packet. This could be caused because of too
few buffers allocated, or because there is insufficient bandwidth on the IO bus. Events
setting this counter cause RXO, the receiver overrun interrupt, to be set. This register
does not increment if receives are not enabled.
Note that these packets are also counted in the Total Packets Received register as well
as in the Total Octets Received register.
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