82583V Datasheet, PDF (50/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Initialization
4.5
4.5.1
Table 23.
Timing Parameters
Timing Requirements
The 82583V requires the following start-up and power state transitions.
Timing Requirements
4.5.2
Parameter
Description
Min
Max
txog
tPWRGD-
CLK
tPVPGL
Tpgcfg
td0mem
tl2pg
tl2clk
Tclkpg
Tpgdl
Xosc stable from power stable
10 ms
PCIe clock valid to PCIe power good
100 μs -
Power rails stable to PCIe PE_RST_N
inactive
100 ms -
External PE_RST_N signal to first
configuration cycle.
100 ms
Device programmed from D3h to D0
state to next device access
10 ms
L2 link transition to PE_RST_N
assertion
0 ns
L2 link transition to removal of PCIe
reference clock
100 ns
PE_RST_N assertion to removal of PCIe
reference clock
0 ns
PE_RST_N assertion time
100 μs
Notes
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
According to PCI power
management specification.
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
MDIO and NVM Semaphore
The MDIO and NVM semaphore mechanism resolved possible conflicts between
software and hardware access to the MDIO and NVM (the latter applies only to software
accesses through the EERD register). The mechanism does not block software accesses
to MDIO or the NVM, therefore programmers can enable software to use or ignore this
process at will. For example, software might track the hardware state through other
means (such as, a software state machine) and avoid any MDIO and NVM accesses
when hardware is in configuration states. However, hardware must comply with the
protocol.The EXTCNF_CTRL.MDIO/NVM SW Ownership bit, EXTCNF_CTRL.MDIO MNG
Ownership bit and the EXTCNF_CTRL.MDIO/NVM HW Ownership bit provide a
mechanism for software, manageability and hardware entities to arbitrate for accesses
to MDIO and NVM. Software arbitration for NVM accesses is only required when done
through the EERD register. A request for ownership is registered by writing a 1b into
the respective bit (software writes to the MDIO/NVM SW Ownership bit, manageability
writes to the MDIO MNG Ownership bit and hardware writes to the MDIO/NVM HW
Ownership). The requesting agent is granted access when the same bit is read as 1b
(access is not granted as long as the bit is 0b). The MDIO/NVM SW Ownership and the
MDIO/NVM HW Ownership bits are cleared on reset, while the MDIO MNG Ownership bit
is reset only by LAN_PWR_GOOD (or if the firmware clears it). The 82583 guarantees
that at any given time at most only one bit is 1b. Access is granted when a bit is
actually written with 1b and the other bits are 0b. Once the access completes, the
controlling agent must write a 0b to its ownership bit to enable accesses by the other
agents.
The 82583’s hardware sets the bit while loading the extended configuration area.
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