82583V Datasheet, PDF (112/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.3.8.6
8. Until new data is written to the FLSWDATA register, the Flash clock is paused.
9. Once data is written to the FLSWDATA by the software, the DONE bit in the
FLSWCTL register is cleared and is set after hardware writes it to the Flash.
10. After all bytes are written to the Flash, hardware completes the cycle on the SPI
bus and sets the WRDONE bit in the FLSWCTL register indicating that the entire
burst has completed.
Flash Programming Flow of S0 and S1
Other than initial programming of the Flash device, software and firmware should not
access the configuration sectors: S0 and S1. Any access to the configuration flow
should go to the Shadow RAM via the EEPROM interface registers.
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