82583V Datasheet, PDF (144/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
Note:
Note:
Table 40.
IDE (bit 7) - Interrupt Delay Enable
VLE (bit 6) - VLAN Packet Enable
DEXT (bit 5) - Descriptor extension (0b for legacy mode)
RSV (bit 4) - Reserved
RS (bit 3) - Report status
IC (bit 2) - Insert checksum
IFCS (bit 1) - Insert FCS (CRC)
EOP (bit 0) - End of packet
IDE activates a transmit interrupt delay timer. Hardware loads a countdown register
when it writes back a transmit descriptor that has RS and IDE set. The value loaded
comes from the IDV field of the Interrupt Delay (TIDV) register. When the count
reaches zero, a transmit interrupt occurs if transmit descriptor write-back interrupts
(TXDW) are enabled. Hardware always loads the transmit interrupt counter whenever it
processes a descriptor with IDE set even if it is already counting down due to a
previous descriptor. If hardware encounters a descriptor that has RS set, but not IDE, it
generates an interrupt immediately after writing back the descriptor and clears the
interrupt delay timer. Setting the IDE bit has no meaning without setting the RS bit.
Although the transmit interrupt might be delayed, the descriptor write-back requested
by setting the RS bit is performed without delay unless descriptor write-back bursting is
enabled.
VLE indicates that the packet is a VLAN packet (for example, that the hardware should
add the VLAN Ether type and an 802.1q VLAN tag to the packet).
If the VLE bit is set, the CTRL.VME bit should also be set to enable VLAN tag insertion.
VLAN Tag Insertion Decision Table when VLAN Mode Enabled (CTRL.VME=1b)
Note:
Note:
VLE
0
1
Action
Send generic Ethernet packet. IFCS controls insertion of FCS in normal Ethernet
packets.
Send 802.1Q packet; the Ethernet Type field comes from the VET register and the
VLAN data comes from the special field of the TX descriptor; hardware appends the
FCS/CRC - command should reflect by setting IFCS to 1b.
The DEXT bit identifies this descriptor as either a legacy or an extended descriptor type
and must be set to 0b to indicate legacy descriptor.
When the RS bit is set, hardware writes back the DD bit once the DMA fetch completes.
Descriptors with the null address (0), or zero length, transfer no data. If they have the
RS bit in the command byte set, then the DD field in the status word is written when
hardware processes them. Hardware only sets the DD bit for descriptors with RS set.
The software can set the RS bit in each descriptor or, more likely, in specific descriptors
such as the last descriptor of each packet.
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