82583V Datasheet, PDF (117/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Inline Functions—82583V GbE Controller
TCPCS (bit 5) - TCP checksum calculated on packet
UDPCS (bit 4) - UDP checksum calculated on packet
VP (bit 3) - Packet is 802.1q (matched VET)
Reserved (bit 2) - Reserved
EOP (bit 1) - End of packet
DD (bit 0) - Descriptor done
EOP: Packets that exceed the receive buffer size spans multiple receive buffers. EOP
indicates whether this is the last buffer for an incoming packet. DD indicates whether
hardware is done with the descriptor. When the DD bit is set along with EOP, the
received packet is completely in main memory. Software can determine buffer usage by
setting the status byte to zero before making the descriptor available to hardware, and
checking it for non-zero content at a later time. For multi-descriptor packets, packet
status is provided in the final descriptor of the packet (EOP set). If EOP is not set for a
descriptor, only the Address, Length, and DD bits are valid.
VP: The VP field indicates whether the incoming packet's type matches VET (for
example, if the packet is a VLAN (802.1q) type). It is set if the packet type matches
VET and CTRL.VME is set. For a further description of 802.1q VLANs, see section 7.5.
IPCS TCPCS UDPCS: These bit descriptions are listed in the following table:
TCPCS
0b
1b
UDPCS
0b
0b
1b
1b
IPCS
0b
1b/0b
1b/0b
Functionality
Hardware does not provide checksum offload.
Hardware provides IPv4 checksum offload if IPCS active and TCP
checksum offload. Pass/fail indication is provided in the Error field
– IPE and TCPE.
Hardware provides IPv4 checksum offload if IPCS active and UDP
checksum offload. Pass/Fail indication is provided in the Error field
– IPE and TCPE.
IPv6 packets do not have the IPCS bit set, but might have the TCPCS bit set if the
82583V recognized the TCP or UDP packet.
7.1.3.4
Error Field (8-Bit, Offset 40)
Most error information appears only when the Store-Bad-Packet bit (RCTL.SBP) is set
and a bad packet is received. Figure 29 shows the definition of the possible errors and
their bit positions.
7
6
5
4
3
2
1
0
RXE
IPE
TCPE
CXE
Rsv
SEQ
SE
CE
Figure 29. Receive Errors (RDESC.ERRORS) Layout
RXE (bit 7) - Rx data error
IPE (bit 6) - IPv4 checksum error
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