82583V Datasheet, PDF (260/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.7.27 Multicast Packets Received Count - MPRC (0x0407C; R)
9.2.7.28
Field
MPRC
Bit(s)
31:0
Initial
Value
0x0
Description
Number of multicast packets received.
This register counts the number of good (non-erred) multicast packets received. This
register does not count multicast packets received that fail to pass address filtering nor
does it count received flow control packets. This register only increments if receives are
enabled. This register does not count packets counted by the Missed Packet Count
(MPC) register.
Good Packets Transmitted Count - GPTC (0x04080; R)
9.2.7.29
Field
GPTC
Bit(s)
31:0
Initial
Value
0x0
Description
Number of good packets transmitted.
This register counts the number of good (non-erred) packets transmitted. A good
transmit packet is considered one that is 64 or more bytes in length (from <Destination
Address> through <CRC>, inclusively) in length. This does not include transmitted flow
control packets. This register only increments if transmits are enabled. This register
does not count packets counted by the Missed Packet Count (MPC) register. The
register counts clear as well as secure packets.
Good Octets Received Count - GORCL (0x04088; R)
9.2.7.30 Good Octets Received Count - GORCH (0x0408C; R)
Field
GORCL
GORCH
Bit(s)
31:0
31:0
Initial
Value
0x0
0x0
Description
Number of good octets received – lower 4 bytes.
Number of good octets received – upper 4 bytes.
These registers make up a logical 64-bit register that counts the number of good (non-
erred) octets received. This register includes bytes received in a packet from the
<Destination Address> field through the <CRC> field, inclusively. This register must be
accessed using two independent 32-bit accesses. This register resets whenever the
upper 32 bits are read (GORCH).
In addition, it sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached.
Only packets that pass address filtering are counted in this register. This register only
increments if receives are enabled.
These octets do not include octets in received flow control packets.
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