82583V Datasheet, PDF (108/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
Address 8K
Address 4K
Address 00
LAN Flash
…
Sector 1
Sector 0
Shadow RAM
EEC.SELSHAD
EEPROM
…
EEPROM Interface
Figure 26. NVM Shadow RAM
6.3.6.1
Flash Mode
The 82583V is initialized from the NVM. As part of the initialization sequence, the
82583V copies the 4 KB content of S0 or S1 from the Flash to the shadow RAM. Any
access to the EEPROM interface is directed to the shadow RAM. Following any write
access to the shadow RAM by software or firmware, the data should also be updated in
the Flash. The 82583V maintains a watchdog timer defined by the FLASHT register to
minimize Flash updates. The timer is triggered by any write access to the shadow RAM.
The 82583V updates the Flash from the shadow RAM when the FLASHT timer expires or
when firmware or software request explicitly to update the Flash by setting the FLUPD
bit in the FLA register. The 82583V copies the content of the shadow RAM to the
inactive configuration sector and then makes it the active one. The Flash update
sequence is listed in the steps that follow:
1. Initiates block erase instruction(s) to the inactive sector (the inactive sector is
defined by the inverse value of the SEC1VAL bit in the EEC register).
2. Copy the shadow RAM to the inactive sector while the signature word is copied last.
3. Clear the signature word in the active sector to make it invalid.
4. Toggle the state of the SEC1VAL bit in the EEC register to indicate that the inactive
sector became the active one and visa versa.
Note:
Software should be aware of the fact that actual programming to the Flash might
require a long latency following the write access to the shadow RAM. Software might
poll the FLUDONE bit in the FLCTL register to complete the Flash programming, when
required.
6.3.6.2
EEPROM Mode
When the 82583V is attached to an external EEPROM, any access to the EEPROM
interface is directed to the external EEPROM.
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