82583V Datasheet, PDF (322/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Programing Interface
10.1.5.2.1.8 Header Log, Offset 0x1C
The header log register captures the header for the transaction that generated an error.
This register is 16 bytes.
10.1.5.2.2
Table 55.
Bit Location Attribute
127:0
RO
Default Value
0x0
Description
Header of the defective packet (TLP or DLLP).
Device Serial Number Capability
The PCIe device serial number capability is an optional extended capability that can be
implemented by any PCIe device. The device serial number is a read-only 64-bit value
that is unique for a given PCIe device.
All multi-function devices that implement this capability must implement it for function
0; other functions that implement this capability must return the same device serial
number value as that reported by function 0. The 82583V is not a multi-function
device.
PCIe Device Serial Number Capability Structure
31
0
PCIe Enhanced Capability Header
Serial Number Register (Lower DW)
Serial Number Register (Upper DW)
10.1.5.2.2.1 Device Serial Number Enhanced Capability Header (Offset 0x00)
Figure 48 details the allocation of register fields in the device serial number enhanced
capability header. The Table below provides the respective bit definitions. The Extended
Capability ID for the Device Serial Number Capability is 0003h.
Figure 48.
31
20 19
16 15
0
Next Capability Offset
Capability Version
PCI Express Extended Capability ID
Allocation of Register Fields in the Device Serial Number Enhanced Capability
Header
Bit(s)
Location
Attributes
Description
15:0
RO
19:16
RO
31:20
RO
PCIe Extended Capability ID
This field is a PCI-SIG defined ID number that indicates the nature and format of
the extended capability.
Extended Capability ID for the Device Serial Number Capability is 0x0003.
Capability Version
This field is a PCI-SIG defined version number that indicates the version of the
capability structure present.
Must be 0x1 for this version of the specification.
Next Capability Offset
This field contains the offset to the next PCIe capability structure or 0x000 if no
other items exist in the linked list of capabilities.
For extended capabilities implemented in device configuration space, this offset is
relative to the beginning of PCI compatible configuration space and thus must
always be either 0x000 (for terminating list of capabilities) or greater than 0x0FF.
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