82583V Datasheet, PDF (216/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.2.26 Software Flash Burst Data Register - FLSWDATA (0x1034; RW)
9.2.2.27
Field
NVDATA
Bit(s)
31:0
Default
0x0
Write NVM Data
Data written to the NVM.
Description
Software Flash Burst Access Counter - FLSWCNT (0x1038; RW)
9.2.2.28
Field
Abort
Reserved
NVCNT
Bit(s)
31
30:25
24:0
Default
Description
Abort
Writing a 1b to this bit aborts the current burst operation. It is self-
0b
cleared by the Flash interface block when the Abort command has
been executed. Abort request is not permitted after writing the last
Dword.
0x0
Reserved
NVM Counter
0x0
This counter holds the size of the Flash burst read or write in Dwords
and is also used as the write byte count but in this case it is byte
count.
Flash Opcode Register - FLOP (0x0103C; RW)
9.2.2.29
This register is used by the 82583V to initiate the appropriate instructions to the NVM
device.
FEEP Auto Load - FLOL (0x01050; RW)
9.2.3
9.2.3.1
Field
RAM_PWR_
SAVE_EN
Reserved
Reserve
Bit(s)
0
7:1
31:8
Default
Description
1b
When set to 1b, enables reduced power consumption by clock gating
the 82583V RAMs.
0x0
Auto loaded from NVM 0x11 bits 7:1.
0x0
Reserved
PCIe Register Descriptions
3GIO Control Register - GCR (0x05B00; RW)
Field
Bit(s)
Disable_
timeout_
31
mechanism
Self_test_
result
30
Gio_good_l0s 29
Gio_dis_rd_
err
28
Initial
Value
0b
0b
0b
0b
Description
If set, the PCIe time-out mechanism is disabled.
If set, a self-test result finished successfully.
Force good PCIe L0s training.
Disable running disparity error of PCIe 108b decoders.
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