82583V Datasheet, PDF (165/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Inline Functions—82583V GbE Controller
7.5
7.5.1
Note:
Write to Clear
The ICR register clears specific interrupt cause bits in the register after writing 1b to
those bits. Any bit that was written with a 0b remains unchanged.
Read to clear
All bits in the ICR register are cleared on a read to ICR.
802.1q VLAN Support
The 82583V provides several specific mechanisms to support 802.1q VLANs:
• Optional adding (for transmits) and ping (for receives) of IEEE 802.1q VLAN tags.
• Optional ability to filter packets belonging to certain 802.1q VLANs.
802.1q VLAN Packet Format
The following diagram compares an untagged 802.3 Ethernet packet with an 802.1q
VLAN tagged packet:
802.3 Packet
DA
SA
Type/Length
Data
CRC
#Octets
6
6
2
46-1500
4
802.1q VLAN
Packet
DA
SA
802.1q Tag
Type/Length
Data
CRC*
#Octets
6
6
4
2
46-1500
4
The CRC for the 802.1q tagged frame is re-computed, so that it covers the entire
tagged frame including the 802.1q tag header. Also, maximum frame size for an 802.1q
VLAN packet is 1522 octets as opposed to 1518 octets for a normal 802.3z Ethernet
packet.
7.5.1.1
802.1q Tagged Frames
For 802.1q, the Tag Header field consists of four octets comprised of the Tag Protocol
Identifier (TPID) and Tag Control Information (TCI); each taking two octets. The first
16 bits of the tag header makes up the TPID. It contains the protocol type, which
identifies the packet as a valid 802.1q tagged packet.
The two octets making up the TCI contain three fields:
• User Priority (UP)
• Canonical Form Indicator (CFI). Should be 0b for transmits. For receives, the
device has the capability to filter out packets that have this bit set. See the CFIEN
and CFI bits in the RCTL described in section 9.2.5.1.
• VLAN Identifier (VID)
165