82583V Datasheet, PDF (255/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.7.9
Collision Count - COLC (0x04028; R)
9.2.7.10
Field
COLC
Bit(s)
31:0
Initial
Value
0x0
Description
Total number of collisions experienced by the transmitter.
This register counts the total number of collisions seen by the transmitter. This register
only increments if transmits are enabled and the device is in half-duplex mode. This
register applies to clear as well as secure traffic.
Defer Count - DC (0x04030; R)
9.2.7.11
Field
CDC
Bit(s)
31:0
Initial
Value
0x0
Number of defer events.
Description
This register counts defer events. A defer event occurs when the transmitter cannot
immediately send a packet due to the medium being busy either because:
• Another device is transmitting
• The IPG timer has not expired
• Hhalf-duplex deferral events
• Reception of XOFF frames
• The link is not up
This register only increments if transmits are enabled. The behavior of this counter is
slightly different in the 82583V relative to previous devices. For the 82583V, this
counter does not increment for streaming transmits that are deferred due to TX IPG.
Transmit with No CRS - TNCRS (0x04034; R)
Field
TNCRS
Bit(s)
31:0
Initial
Value
0x0
Description
Number of transmissions without a CRS assertion from the PHY.
This register counts the number of successful packet transmissions in which the CRS
input from the PHY was not asserted within one slot time of start of transmission from
the MAC. Start of transmission is defined as the assertion of TX_EN to the PHY.
The PHY should assert CRS during every transmission. Failure to do so might indicate
that the link has failed, or the PHY has an incorrect link configuration. This register only
increments if transmits are enabled. This register is only valid when the 82583V is
operating at half duplex.
255