82583V Datasheet, PDF (345/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Design Considerations—82583V GbE Controller
11.7
Note:
11.7.1
• The ground plane beneath a magnetics module should be split. The RJ45 connector
side of the transformer module should have chassis ground beneath it.
• Power delivery traces should be a minimum of 100 mils wide at all places from the
source to the destination. As power flows through pass transistors or regulators,
the traces must be kept wide as well. The distribution of power is better done with
a copper-pore under the PHY. This provides low inductance connectivity to
decoupling capacitors. Decoupling capacitors should be placed as close as possible
to the point of use and should avoid sharing vias with other decoupling capacitors.
Decoupling capacitor placement control should be done for the PHY as well as pass
transistors or regulators.
Device Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability
for selectively enabling or disabling LOM devices. This enables designers more control
over system resource-management, avoid conflicts with add-in NIC solutions, etc. The
82583V provides support for selectively enabling or disabling it.
Device disable is initiated by asserting the asynchronous DEV_OFF_N pin. The
DEV_OFF_N pin has an internal pull-up resistor, so that it can be left not connected to
enable device operation.
The NVM’s Device Disable Power Down En bit enables device disable mode (hardware
default is that the mode is disabled).
While in device disable mode, the PCIe link is in L3 state. The PHY is in power down
mode. Output buffers are tri-stated.
Assertion or deassertion of PCIe PE_RST_N does not have any effect while the 82583V
is in device disable mode (that is, the 82583V stays in the respective mode as long as
DEV_OFF_N is asserted). However, the 82583V might momentarily exit the device
disable mode from the time PCIe PE_RST_N is de-asserted again and until the NVM is
read.
During power-up, the DEV_OFF_N pin is ignored until the NVM is read. From that point,
the 82583V might enter device disable if DEV_OFF_N is asserted.
The DEV_OFF_N pin should maintain its state during system reset and system sleep
states. It should also insure the proper default value on system power up. For example,
a designer could use a GPIO pin that defaults to 1b (enable) and is on system suspend
power. For example, it maintains the state in S0-S5 ACPI states).
BIOS Handling of Device Disable
Assume that in the following power-up sequence the DEV_OFF_N signal is driven high
(or it is already disabled)
1. The PCIe is established following the GIO_PWR_GOOD.
2. BIOS recognizes that the entire 82583V should be disabled.
3. The BIOS drives the DEV_OFF_N signal to the low level.
4. As a result, the 82583V samples the DEV_OFF_N signals and enters either the
device disable mode.
5. The BIOS could put the link in the Electrical IDLE state (at the other end of the PCIe
link) by clearing the Link Disable bit in the Link Control register.
6. BIOS might start with the device enumeration procedure (the entire 82583V
functions are invisible).
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