82583V Datasheet, PDF (173/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Power Management and Delivery—82583V GbE Controller
Note:
The AUX Power PM Enable bit in the PCIe Device Control register determines if the
82583V complies with the auxiliary power regime defined in the PCIe specification. If
set, the 82583V might consume higher power for any purpose (such as, even if PME_En
is not set).
If the AUX Power PM Enable bit of the PCIe Device Control register is cleared, higher
power consumption is determined by the PCI-PM legacy PME_En bit in the Power
Management Control / Status Register (PMCSR).
In the current implementation, the AUX Power PM Enable bit is hardwired to 0b.
8.4.3
Table 45.
Power Limits by Certain Form Factors
Table 45 lists the power limitations introduced by different form factors.
Power Limits by Form Factor
Note:
Main
Auxiliary (aux enabled)
Auxiliary (aux disabled)
LOM
3 A @ 3.3 V dc
375 mA @ 3.3 V dc
20 mA @ 3.3 V dc
Form Factor
PCIe NIC (x1 connector)
3 A @ 3.3 V dc
375 mA @ 3.3 V dc
1. This auxiliary current limit only applies when the primary 3.3 V dc voltage source is
not available (such as, the NIC is in a low power D3 state.
2. The 82583V exceeds the allowed power consumption in GbE speed. It therefore
cannot run from aux power, restricting the 82583V speed in Dr state.
The 82583V therefore implements two NVM bits to disable GbE operation in certain
cases:
1. The Disable 1000 NVM bit disables 1000 Mb/s operation under all conditions.
2. The Disable 1000 in non-D0a CSR bit disables 1000 Mb/s operation in non-D0a
states. If Disable 1000 in non-D0a is set, and the 82583V is at GbE speed on entry
to a non-D0a state, then the device removes advertisement for 1000 Mb/s and
auto-negotiates. The Disable 1000 in non-D0a bit is loaded from the NVM.
The 82583V restarts link auto-negotiation each time it transitions from a state where
GbE speed is enabled to a state where GbE speed is disabled, or vice versa. For
example, if Disable 1000 in non-D0a is set but Disable 1000 is clear, the 82583V
restarts link auto-negotiation on transition from D0 state to D3 or Dr states.
8.4.4
Power States
8.4.4.1
D0 Uninitialized State
The D0u state is a low-power state used after PE_RST_N is de-asserted following a
power up (cold or warm), on hot reset (in-band reset through a PCIe physical layer
message), or on D3 exit.
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