82583V Datasheet, PDF (312/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Programing Interface
10.1.4.3
Message Control Offset 0xD2, (R/W)
The register fields are listed in the following table.
10.1.4.4
10.1.4.5
10.1.4.6
10.1.5
Bits
Default R/W
0
0b
R/W
3:1
000b
RO
6:4
000b
RO
7
1b
RO
15:8 0x0
RO
Description
MSI Enable
If set to 1b, MSI. In this case, the 82583V generates MSI for interrupt
assertion instead of INTx signaling.
Multiple Message Capable
The 82583V indicates a single requested message.
Multiple Message Enable
The 82583V returns 000b to indicate that it supports a single message.
64-bit capable. A value of 1b indicates that the 82583V is capable of
generating 64-bit message addresses.
Reserved, reads as 0b.
Message Address Low Offset 0xD4, (R/W)
Written by the system to indicate the lower 32 bits of the address to use for the MSI
memory write transaction. The lower two bits always returns 0b regardless of the write
operation.
Message Address High, Offset 0xD8, (R/W)
Written by the system to indicate the upper 32 bits of the address to use for the MSI
memory write transaction.
Message Data, Offset 0xDC, (R/W)
Written by the system to indicate the lower 16 bits of the data written in the MSI
memory write Dword transaction. The upper 16 bits of the transaction are written as
0b.
PCIe Configuration Registers
PCIe provides two mechanisms to support native features:
• PCIe defines a PCIe capability pointer indicating support for PCIe.
• PCIe extends the configuration space beyond the 256 bytes available for PCI to
4096 bytes.
Initialization values of the configuration registers are marked in parenthesis.
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