82583V Datasheet, PDF (63/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Non-Volatile Memory (NVM) Map—82583V GbE Controller
5.1.1.15 PCIe Init Configuration 2 Word (Word 0x19)
Bit
15
14
13
12
11:8
7:0
Name
DLLP timer
enable
Reserved
Reserved
SER_EN
ExtraNFTS
NFTS
Hardware
Default
NVM
Image
Setting
Description
0b
0b
1b
0b
0x1
0x50
0b
0b
1b
1b
0x1
0x50
When set, enables the DLLP timer counter.
Reserved, must be set to 0b.
Reserved, must be set to 1b.
When set to 1b, the serial number capability is enabled.
Extra NFTS (number of fast training signal), which is
added to the original requested number of NFTS (as
requested by the upstream component).
Number of special sequence for L0s transition to L0.
5.1.1.16 PCIe Init Configuration 3 Word (Word 0x1A)
Bit
15
14
13
12
11:10
9
8
7
6
5
4
Name
Hardware
Default
NVM
Image
Setting
Description
Master_Enable 0b
Scram_dis
0b
Ack_Nak_Sch 0b
Cache_Lsize
0b
PCIE_Cap
01b
IO_Sup
1b
Packet_Size
1b
Reserved
0b
Reserved
0b
Reserved
0b
Reserved
0b
0b
When set to 1b, this bit enables the PHY to be a master
(upstream component/cross link functionality).
0b
Scrambling Disable
When set to 1b, this bit disables the PCIe LFSR scrambling.
ACK/NAK Scheme
0b
0b = Scheduled for transmission following any TLP.
1b = Scheduled for transmission according to time outs
specified in the PCIe specification.
Cache Line Size
0b = 64 bytes.
0b
1b = 128 bytes.
Note: The value loaded must be equal to the actual cache
line size used by the platform, as configured by system
software.
01b
PCIe Capability Version
I/O Support (Effect I/O BAR Request)
1b
0b = I/O is not supported.
1b = I/O is supported.
Default Packet Size
1b
0b = 128 bytes.
1b = 256 bytes.
0b
Reserved, must be set to 0b.
0b
Reserved, must be set to 0b.
1b
Reserved.
1b
Reserved.
63