82583V Datasheet, PDF (245/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.6
9.2.6.1
Transmit Register Descriptions
Transmit Control Register - TCTL (0x00400; RW)
Field
Reserved
EN
Reserved
PSP
CT
COLD
SWXOFF
PBE
RTLC
UNORTX
TXDSCMT
MULR
Bit(s)
0
1
2
3
11:4
21:12
22
23
24
25
27:26
28
Initial
Value
0b
0b
0b
1b
0x0
0b
0b
0b
0b
1b
Description
Reserved
Write as 0b for future compatibility.
Enable
The transmitter is enabled when this bit is set to 1b. Writing this bit to
0b stops transmission after any in progress packets are sent. Data
remains in the transmit FIFO until the device is re-enabled. Software
should combine this with a reset if the packets in the FIFO need to be
flushed.
Reserved
Reads as 0b. Should be written to 0b for future compatibility.
Pad short packets (with valid data, NOT padding symbols).
0b = do not pad
1b = pad.
Padding makes the packet 64 bytes. This is not the same as the
minimum collision distance.
If padding of short packet is allowed, the value in TX descriptor length
field should be not less than 17 bytes.
Collision Threshold
This determines the number of attempts at re-transmission prior to
giving up on the packet (not including the first transmission attempt).
While this can be varied, it should be set to a value of 15 in order to
comply with the IEEE specification requiring a total of 16 attempts.
The Ethernet back-off algorithm is implemented and clamps to the
maximum number of slot times after 10 retries. This field only has
meaning while in half-duplex operation.
Collision Distance
Specifies the minimum number of byte times that must elapse for
proper CSMA/CD operation. Packets are padded with special symbols,
not valid data bytes. Hardware checks and pads to this value plus one
byte even in full-duplex operation.
Software XOFF Transmission
When set to 1b, the device schedules the transmission of an XOFF
(PAUSE) frame using the current value of the pause timer. This bit self
clears upon transmission of the XOFF frame.
Packet Burst Enable
The 82583V does not support packet bursting for 1 Gb/s half-duplex
transmit operation. This bit must be set to 0b.
Re-Transmit on Late Collision
Enables the device to re-transmit on a late collision event. This bit is
ignored in full-duplex mode.
Under run No Re-Transmit
Tx Descriptor Minimum Threshold
Multiple Request Support
This bit defines the number of read requests the 82583V issues for
transmit data. When set to 0b, the 82583V submits only one request
at a time, When set to 1b, the 82583V might submit up to four
concurrent requests. The software device driver must not modify this
register when the Tx head register is not equal to the tail register.
This bit is loaded from the NVM word 0x24/0x14.
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