82583V Datasheet, PDF (230/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.4.6
Interrupt Auto Clear- EIAC (0x000DC; RW)
9.2.4.7
Field
Reserved
Reserved
Reserved
Bit(s)
19:0
24:20
31:25
Initial
Value
0x0
0x0
0x0
Reserved
Reserved
Reserved
Description
Interrupt Acknowledge Auto–Mask - IAM (0x000E0; RW)
9.2.5
9.2.5.1
Field
IAM_VALUE
Bit(s)
31:0
Initial
Value
0x0
Description
When the CTRL_EXT.IAME bit is set and the ICR.INT_ASSERT=1b, an
ICR read or write has the side effect of writing the contents of this
register to the IMC register.
Receive Register Descriptions
Receive Control Register - RCTL (0x00100; RW)
Field
Reserved
EN
SBP
UPE
MPE
LPE
Bit(s)
0
1
2
3
4
5
Initial
Value
0b
0b
0b
0b
0b
0b
Description
Reserved
This bit represented as a hardware reset of the receive-related
portion of the device in previous controllers, but is no longer
applicable. Only a full device reset CTRL.RST is supported. Write as 0b
for future compatibility.
Enable
The receiver is enabled when this bit is set to 1b. Writing this bit to
0b, stops reception after receipt of any in progress packet. All
subsequent packets are then immediately dropped until this bit is set
to 1b.
Store Bad Packets
0b = Do not store
1b = Store.
Note that CRC errors before the SFD are ignored. Any packet must
have a valid SFD (RX_DV with no RX_ER in the GMII/MII interface) in
order to be recognized by the device (even bad packets)
Unicast Promiscuous Enable
0b = Disabled.
1b = Enabled.
Multicast Promiscuous Enable
0b = Disabled.
1b = Enabled.
Long Packet Enable.
0b = Disabled (always set to 0b).
1b = Enabled (not supported).
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