82583V Datasheet, PDF (336/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Design Considerations
Minimizing the amount of space needed for the Ethernet LAN interface is important
because other interfaces compete for physical space on a motherboard near the
connector. The Ethernet LAN circuits need to be as close as possible to the connector.
Keep silicon traces at least 1" from edge of
PB (2" is preferred).
Keep LAN silicon 1" - 4" from LAN connector.
Integrated
RJ-45
w/LAN
Magnetics
LAN
Silicon
Keep minimum distance between differential pairs
more than seven times the dielectric thickness away
from each other and other traces, including NVM
traces and parallel digital traces.
Note: Figure 55 represents a 10/100 diagram. Use the same design considerations for the two
differential pairs not shown for gigabit implementations.
Figure 55.
General Placement Distances for 1000 BASE-T Designs
Figure 55 shows some basic placement distance guidelines. Figure 55 shows two
differential pairs, but can be generalized for a Gigabit system with four analog pairs.
The ideal placement for the Ethernet silicon would be approximately one inch behind
the magnetics module.
While it is generally a good idea to minimize lengths and distances, Figure 55 also
illustrates the need to keep the LAN silicon away from the edge of the board and the
magnetics module for best EMI performance.
11.5.5.2 Layout Guidelines for Use with Integrated and Discrete Magnetics
Layout requirements are slightly different when using discrete magnetics.
These include:
• Ground cut for HV installation (not required for integrated magnetics)
• A maximum of two (2) vias
• Turns less than 45°
• Discrete terminators
Figure 56 shows a reference layout for discrete magnetics.
336