82583V Datasheet, PDF (237/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Note:
Note:
9.2.5.11
This feature operates by initiating a countdown timer upon successfully receiving each
packet to system memory. If a subsequent packet is received before the timer expires,
the timer is re-initialized to the programmed value and re-starts its countdown. If the
timer expires due to not having received a subsequent packet within the programmed
interval, pending receive descriptor write backs are flushed and a receive timer
interrupt is generated.
Setting the value to zero represents no delay from a receive packet to the interrupt
notification, and results in immediate interrupt notification for each received packet.
Writing this register with FPD set initiates an immediate expiration of the timer, causing
a write back of any consumed receive descriptors pending write back, and results in a
receive timer interrupt in the ICR.
Receive interrupts due to a Receive Absolute Timer (RADV) expiration cancels a
pending RDTR interrupt. The RDTR countdown timer is reloaded but halted, so as to
avoid generation of a spurious second interrupt after the RADV has been noted, but can
be restarted by a subsequent received packet.
FPD is self clearing.
This register's address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00108.
Receive Descriptor Control - RXDCTL (0x02828; RW)
Note:
Field
PTHRESH
Rsv
HTHRESH
Reserved
Rsv
WTHRESH
Rsv
GRAN
Rsv
Bit(s)
5:0
7:6
13:8
14
15
21:16
23:22
24
31:25
Initial
Value
0x00
0x00
0x00
0b
0b
0x01
00b
0b
0x0
Description
Prefetch Threshold
Reserved
Host Threshold
Reserved
Reserved
Write-Back Threshold
Reserved
Granularity
Units for the thresholds in this register.
0b = Cache lines.
1b = Descriptors.
Reserved
Any value written to RXDCTL0 is automatically written to RXDCTL1. Writes to RXDCTL1
affects RXDCTL1 only.
This register controls the fetching and write back of receive descriptors. The three
threshold values are used to determine when descriptors are read from and written to
host memory. The values can be in units of cache lines or descriptors (each descriptor
is 16 bytes) based on the GRAN flag. If GRAN=0b (specifications are in cache-line
granularity), the thresholds specified (based on the cache line size specified in the PCIe
header CLS field) must not represent greater than 31 descriptors.
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