82583V Datasheet, PDF (297/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Note:
9.2.9.3
This register stores the head pointer of the on–chip receive data FIFO. Since the
internal FIFO is organized in units of 64-bit words, this field contains the 64-bit offset of
the current receive FIFO head. So a value of 0x8 in this register corresponds to an
offset of eight Qwords or 64 bytes into the receive FIFO space. This register is available
for diagnostic purposes only, and should not be written during normal operation.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x08000. In addition, with the 82583V, the value in this register contains the
offset of the receive FIFO head relative to the beginning of the entire PBM space.
Alternatively, with previous devices, the value in this register contains the relative
offset to the beginning of the receive FIFO space (within the PBM space).
Receive Data FIFO Tail Register - RDFT (0x02418; RW)
Note:
9.2.9.4
Field
FIFO Tail
Reserved
Bit(s)
12:0
31:13
Initial
Value
0x0
0x0
Description
Receive FIFO Tail pointer.
Reads as 0x0. Should be written to 0x0 for future compatibility.
This register stores the tail pointer of the on–chip receive data FIFO. Since the internal
FIFO is organized in units of 64 bit words, this field contains the 64 bit offset of the
current Receive FIFO Tail. So a value of “0x8” in this register corresponds to an offset of
8 QWORDS or 64 bytes into the Receive FIFO space. This register is available for
diagnostic purposes only, and should not be written during normal operation.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x08008. In addition, with the 82583V, the value in this register contains the
offset of the receive FIFO tail relative to the beginning of the entire PBM space.
Alternatively, with previous devices, the value in this register contains the relative
offset to the beginning of the Receive FIFO space (within the PBM space).
Receive Data FIFO Head Saved Register - RDFHS (0x02420; RW)
9.2.9.5
Field
FIFO Head
Reserved
Bit(s)
12:0
31:13
Initial
Value
0x0
0x0
Description
A saved value of the receive FIFO head pointer.
Reads as 0x0. Should be written to 0x0 for future compatibility.
This register stores a copy of the Receive Data FIFO Head register if the internal
register needs to be restored. This register is available for diagnostic purposes only,
and should not be written during normal operation.
Receive Data FIFO Tail Saved Register - RDFTS (0x02428; RW)
Field
FIFO Tail
Reserved
Bit(s)
12:0
31:13
Initial
Value
0x0
0x0
Description
A saved value of the receive FIFO tail pointer.
Reads as 0x0. Should be written to 0x0 for future compatibility.
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