82583V Datasheet, PDF (96/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.2.1.1
6.2.1.2
6.2.2
The internal Gigabit Media Independent Interface (GMII) mode of operation is similar to
MII mode of operation. GMII mode uses the same MDIO/MDC management interface
and registers for PHY configuration as MII mode. These common elements of operation
enable the 82583V MAC and PHY to cooperatively determine a link partner's operational
capability and configure the hardware based on those capabilities.
MDIO/MDC
The 82583V implements an internal IEEE 802.3 MII Management Interface (also known
as the Management Data Input/Output or MDIO Interface) between the MAC and PHY.
This interface provides the MAC and software the ability to monitor and control the
state of the PHY. The internal MDIO interface defines a physical connection, a special
protocol that runs across the connection, and an internal set of addressable registers.
The internal interface consists of a data line (MDIO) and clock line (MDC), which are
accessible by software via the MAC register space.
Software can use MDIO accesses to read or write registers in either GMII or MII mode
by accessing the 82583V's MDIC register (see section 9.2.2.7).
Other MAC/PHY Control and Status
In addition to the internal GMII/MII communication and MDIO interface between the
MAC and the PHY, the 82583V implements a handful of additional internal signals
between MAC and PHY, which provide richer control and features.
• PHY reset - The MAC provides an internal reset to the PHY. This signal combines the
PCI_RST_N input from the PCI bus and the PHY Reset bit of the Device Control
register (CTRL.PHY_RST).
• PHY link status indication - The PHY provides a direct internal indication of link
status (LINK) to the MAC to indicate whether it has sensed a valid link partner.
Unless the PHY has been configured via its MII management registers to assert this
indication unconditionally, this signal is a valid indication of whether a link is
present. The MAC relies on this internal indication to reflect the STATUS.LU status
as well as to initiate actions such as generating interrupts on link status changes,
re-initiating link speed sense, etc.
• PHY duplex indication - The PHY provides a direct internal indication to the MAC of
its resolved duplex mode (FDX). Normally, auto-negotiation by the PHY enables the
PHY to resolve full/duplex communications with the link partner (except when the
PHY is forced through MII register settings). The MAC normally uses this signal
after a link loss/restore to ensure that the MAC is configured consistently with the
re-linked PHY settings. This indication is effectively visible through the MAC register
bit STATUS.FD, each time MAC speed has not been forced.
• PHY speed indication(s) - The PHY provides direct internal indications (SPD_IND) to
the MAC of its negotiated speed (10/100/1000 Mb/s). The result of this indication is
effectively visible through the MAC register bits STATUS.SPEED each time MAC
speed has not been forced.
• MAC Dx power state indication - The MAC indicates its ACPI power state
(PWR_STATE) to the PHY to enable it to perform intelligent power-management
(provided that the PHY power-management is enabled in the MAC CTRL register).
Duplex Operation for Copper PHY/GMII/MII Operation
The 82583V supports half-duplex and full-duplex 10/100 Mb/s MII mode or 1000 Mb/s
GMII mode.
Configuring the duplex operation of the 82583V can either be forced or determined via
the auto-negotiation process. See section 6.2.3 for details on link configuration setup
and resolution.
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