82583V Datasheet, PDF (17/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Pin Interface—82583V GbE Controller
2.2
2.3
Pull-Up/Pull-Down Resistors and Strapping Options
• As stated in the Name and Function table columns, the internal Pull-Up/Pull-Down
(PU/PD) resistor values are 30 KΩ ± 50%.
• Only relevant (digital) pins are listed; analog or bias and power pins have specific
considerations listed in Section 3.0.
• NVMT and AUX_PWR are used for a static configuration. They are sampled while
PE_RST_N is active and latched when PE_RST_N is deasserted. At other times,
they revert to their standard usage.
Signal Type Definition
2.3.1
In
Out (O)
T/s
S/t/s
O/d
A-in
A-out
B
PCIe
Input is a standard input-only signal.
Totem pole output is a standard active driver.
Tri-State is a bi-directional, tri-state input/output pin.
Sustained tri-state is an active low tri-state signal owned and driven by one and only one agent
at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before
letting it float. A new agent cannot start driving an s/t/s signal any sooner than one clock after
the previous owner tri-states it.
Open drain enables multiple devices to share as a wire-OR.
Analog input signals.
Analog output signals.
Input bias.
Table 6.
PCIe
Symbol
PECLKp
PECLKn
PE_Tp
PE_Tn
Lead #
26
25
21
20
Type
Op
Mode
Name and Function
A-in
A-out
Input
PCIe Differential Reference Clock In
This pin receives a 100 MHz differential clock input. This clock
is used as the reference clock for the PCIe Tx/Rx circuitry and
by the PCIe core PLL to generate a 125 MHz clock and 250
MHz clock for the PCIe core logic.
Output
PCIe Serial Data Output
Serial differential output link in the PCIe interface running at
2.5 Gb/s. This output carries both data and an embedded 2.5
GHz clock that is recovered along with data at the receiving
end.
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