82583V Datasheet, PDF (204/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
Field
Bit(s)
Initial
Value
SPD_BYPS
15
0b
Reserved
16
0b¹
RO_DIS
17
0b
Reserved
18
0b
DMA Dynamic
Gating Enable
19
0b¹
PHY Power
Down Enable
20
1b¹
Reserved
21
0b¹
Tx LS Flow
22
0b¹
Tx LS
23
0b¹
EIAME
24
0b
Reserved
26:25
00b
IAME
27
0b
DRV_LOAD
28
0b
INT_TIMERS_
CLEAR_ENA
29
0b
Reserved
30
0b
PBA_Supportr 31
0b
1. These bits are read from the NVM.
Description
Speed Select Bypass
When set to 1b, all speed detection mechanisms are bypassed and
the device is immediately set to the speed indicated by CTRL.SPEED.
This provides a method for software to have full control of the speed
settings of the device as well as when the change takes place by
overriding the hardware clock switching circuitry.
Reserved
Should be set to 0b.
Relaxed Ordering Disable
When set to 1b, the device does not request any relaxed ordering
transactions regardless of the state of bit 4 (Enable Relaxed Ordering)
in the PCIe Device Control register. When this bit is cleared and bit 4
of the PCIe Device Control register is set, the device requests relaxed
ordering transactions as described in Section 6.1.3.8.2.
Reserved
When set, this bit enables dynamic clock gating of the DMA and MAC
units.
When set, this bit enables the PHY to enter a low-power state.
Reserved
Should be set for correct TSO functionality. Refer to Section 7.3.
Should be cleared for correct TSO functionality. Refer to Section 7.3.
Extended Interrupt Auto Mask Enable
EIAM is used only upon a read of the EICR register.
Reserved
When the IAME (interrupt acknowledge auto-mask enable) bit is set,
a read or write to the ICR register has the side effect of writing the
value in the IAM register to the IMC register. When this bit is 0b, the
feature is disabled.
Driver Loaded
This bit should be set by the software device driver after it was
loaded, Cleared when the software device driver unloads or PCIe soft
reset.
When set, this bit enables the clearing of the interrupt timers
following an IMS clear. In this state, successive interrupts occur only
after the timers expire again. When cleared, successive interrupts
following IMS clear might happen immediately.
Reserved
Reads as 0b.
PBA Support
The 82583V behaves in a way supporting legacy INT-x interrupts.
Should be cleared when working in INT-x or MSI mode.
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