82583V Datasheet, PDF (161/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Inline Functions—82583V GbE Controller
7.4.3
The interrupt causes include:
• The receive and transmit related interrupts.
• Other bits in this register are the legacy indication of interrupts as the MDIC
completes a link status change. There is a specific Other Cause bit that is set if one
of these bits are set.
Interrupt Cause Set Register (ICS)
This registers allows triggering an immediate interrupt by software, By writing 1b to
bits in ICS the corresponding bits in ICR is set Used usually to rearm interrupts the
software didn't have time to handle in the current interrupt routine.
Interrupt Mask Set and Read Register (IMS) and Interrupt Mask Clear
Register (IMC)
Interrupts appear on PCIe only if the interrupt cause bit is a one and the corresponding
interrupt mask bit is a one. Software blocks assertion of an interrupt by clearing the
corresponding bit in the mask register. The cause bit stores the interrupt event
regardless of the state of the mask bit. Clear and set make this register more thread
safe by avoiding a read-modify-write operation on the mask register. The mask bit is
set for each bit written to a one in the set register and cleared for each bit written in
the clear register. Reading the set register (IMS) returns the current mask register
value.
Interrupt Auto Clear Enable Register (EIAC)
Bits 24:20 in this register enables clearing of the corresponding bit in ICR following
interrupt generation. When a bit is set, the corresponding bit in ICR and in IMS is
automatically cleared following an interrupt.
Bits in the ICR that are not set in EIAC need to be cleared with ICR read or ICR write-
to-clear.
Interrupt Auto Mask Enable register (IAM)
Each bit in this register enables setting of the corresponding bit in IMS following write
to-clear to ICR.
Interrupt Moderation
The 82583V implements interrupt moderation to reduce the number of interrupts
software processes. The moderation scheme is based on a timer called ITR Interrupt
Throttle register). In general terms, the ITR defines an interrupt rate by defining the
time interval between consecutive interrupts.
The number of ITR registers is:
• A single ITR is used (ITR).
Software uses ITR to limit the rate of delivery of interrupts to the host CPU. It provides
a guaranteed inter-interrupt delay between interrupts asserted by the network
controller, regardless of network traffic conditions.
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