82583V Datasheet, PDF (248/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
Note:
9.2.6.5
This register contains the lower bits of the 64-bit descriptor base address. The lower
four bits are ignored. The transmit descriptor base address must point to a 16-byte
aligned block of data.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00420.
Transmit Descriptor Base Address High - TDBAH (0x03804; RW)
Note:
9.2.6.6
Field
TDBAH
Bit(s)
31:0
Initial
Value
X
Description
Transmit Descriptor Base Address [63:32]
This register contains the upper 32 bits of the 64-bit descriptor base address.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00424.
Transmit Descriptor Length - TDLEN (0x03808; RW)
Note:
9.2.6.7
Field
0
LEN
Reserved
Bit(s)
6:0
19:7
31:20
Initial
Value
0x0
0x0
0x0
Description
Ignore on write. Reads back as 0x0.
Descriptor Length
Reads as 0x0. Should be written to 0x0.
This register contains the descriptor length and must be 128-byte aligned.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00428.
Transmit Descriptor Head - TDH (0x03810; RW)
Note:
Field
TDH
Reserved
Bit(s)
15:0
31:16
Initial
Value
0x0
0x0
Description
Transmit Descriptor Head
Reserved
Should be written with 0x0.
This register contains the head pointer for the transmit descriptor ring. It points to a
16-byte datum. Hardware controls this pointer. The only time that software should
write to this register is after a reset (hardware reset or CTRL.RST) and before enabling
the transmit function (TCTL.EN).
If software were to write to this register while the transmit function was enabled, the
on-chip descriptor buffers might be invalidated and the hardware could be become
unstable.
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