82583V Datasheet, PDF (46/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Initialization
4.3.2
Timing Diagram
Power
txo
g
1
Xosc
Power-On-Reset
(internal)
PCIe reference clock
PERST#
NVM Load
PHY State
PCIe Link up
Wake
D-State
tpp
g
2
tPWRGD
-CLK ₆
tPVP
GL 7
Powered-down
8
3
tee
Auto Ext.
Read Conf.
4
Active / Down
5
tee
Auto Ext.
Read Conf.
9
tpgtrn
tpgcfg tpgres
10
11 12
13
L0
Dr
D0u
D0a
Figure 15.
Table 21.
Power-Up Timing Diagram
Notes to Power-Up Timing Diagram
Note
1
2
3
4
5
6
7
8
9
10
11
12
13
Xosc is stable txog after power is stable
Internal reset is released after all power supplies are good and tppg after Xosc
is stable.
An NVM read starts on the rising edge of the internal reset or Internal Power
On Reset#.
After reading the NVM, PHY might exit power down mode.
APM wake up might be enabled based on NVM contents.
The PCIe reference clock is valid tPWRGD-CLK before the de-assertion of
PE_RST_N (according to PCIe specification).
PE_RST_N is de-asserted tPVPGL after power is stable (according to PCIe
specification).
De-assertion of PE_RST_N causes the NVM to be re-read, asserts PHY power-
down, and disables Wake Up.
After reading the NVM, PHY exits power-down mode.
Link training starts after tpgtrn from PE_RST_N de-assertion.
A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-
assertion.
A first PCI configuration response can be sent after tpgres from PE_RST_N de-
assertion
Writing a 1b to the Memory Access Enable bit in the PCI Command register
transitions the device from D0u to D0 state.
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