82583V Datasheet, PDF (208/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.2.8
Flow Control Address Low - FCAL (0x00028; RW)
Note:
9.2.2.9
Field
FCAL
Bit(s)
31:0
Initial
Value
X
Description
Flow Control Address Low
Flow control packets are defined by 802.3X to be either a unique multicast address or
the station address with the EtherType field indicating pause. Hardware compares
incoming packets against the FCA register value to determine if it should pause its
output.
This register contains the lower bits of the internal 48-bit flow control Ethernet address.
All 32 bits are valid. Software can access the High and Low registers as a register pair if
it can perform a 64-bit access to the PCIe bus. This register should be programmed
with 0x00_C2_80_01. The complete flow control multicast address is:
0x01_80_C2_00_00_01; where 01 is the first byte on the wire, 80 is the second, etc.
Any packet matching the contents of {FCAH, FCAL, FCT} when CTRL.RFCE is set is
acted on by the 82583V. Whether flow control packets are passed to the host
(software) depends on the state of the RCTL.DPF bit and whether the packet matches
any of the normal filters.
Flow Control Address High - FCAH (0x0002C; RW)
Note:
Field
FCAH
Reserved
Bit(s)
15:0
31:16
Initial
Value
X
0x0
Description
Flow Control Address High
Reserved
Reads as 0x0.
This register contains the upper bits of the 48-bit flow control Ethernet address. Only
the lower 16 bits of this register have meaning. The complete flow control address is
{FCAH, FCAL}. This register should be programmed with 0x01_00. The complete flow
control multicast address is: 0x01_80_C2_00_00_01; where 01 is the first byte on the
wire, 80 is the second, etc.
At the time of the original implementation, the flow control multicast address was not
defined and thus hardware provided programmability. Since then, the final release of
the 802.3x standard has reserved the following multicast address for MAC control
frames: 0x01-80-C2-00-00-01.
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