82583V Datasheet, PDF (246/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
Note:
9.2.6.2
Field
RRTHRESH
Reserved
Bit(s)
30:29
31
Initial
Value
01b
0b
Description
Read Request Threshold
These bits define the threshold size for the intermediate buffer to
determine when to send the read command to the packet buffer.
Threshold is defined as follows:
RRTHRESH = 00b threshold = 2 lines of 16 bytes
RRTHRESH = 01b threshold = 4 lines of 16 bytes
RRTHRESH = 10b threshold = 8 lines of 16 bytes
RRTHRESH = 11b threshold = No threshold (transfer data after all of
the request is in the RFIFO)
Reserved
Reads as 0b. Should be written to 0b for future compatibility.
Two fields deserve special mention: CT and COLD. Software might choose to abort
packet transmission in less than the Ethernet mandated 16 collisions. For this reason,
hardware provides CT.
Wire speeds of 1000 Mb/s result in a very short collision radius with traditional
minimum packet sizes. COLD specifies the minimum number of bytes in the packet to
satisfy the desired collision distance. It is important to note that the resulting packet
has special characters appended to the end. These are NOT regular data characters.
Hardware strips special characters for packets that go from 1000 Mb/s environments to
100 Mb/s environments. Note that the hardware evaluates this field against the packet
size in full duplex as well.
While 802.3x flow control is only defined during full duplex operation, the sending of
pause frames via the SWXOFF bit is not gated by the duplex settings within the device.
Software should not write a 1b to this bit while the device is configured for half-duplex
operation.
RTLC configures the 82583V to perform retransmission of packets when a late collision
is detected. Note that the collision window is speed dependent: 64 bytes for 10/
100 Mb/s and 512 bytes for 1000 Mb/s operation. If a late collision is detected when
this bit is disabled, the transmit function assumes the packet is successfully
transmitted. This bit is ignored in full-duplex mode.
Transmit IPG Register - TIPG (0x00410; RW)
Field
IPGT
IPGR1
IPGR2
Bit(s)
9:0
19:10
29:20
Initial
Value
0x8
0x8
0x6
Description
IPG Transmit Time
Measured in increments of the MAC clock:
8 ns @ 1 Gb/s
80 ns @ 100 Mb/s
800 ns @ 10 Mb/s.
IPG Receive Time 1
Measured in increments of the MAC clock:
8 ns @ 1 Gb/s
80 ns @ 100Mb/s
800 ns @ 10 Mb/s.
IPG Receive Time 2
Measured in increments of the MAC clock:
8 ns @ 1 Gb/s
80 ns @ 100 Mb/s
800 ns @ 10 Mb/s.
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