82583V Datasheet, PDF (64/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Non-Volatile Memory (NVM) Map
Bit
3:2
1
0
Name
Hardware
Default
NVM
Image
Setting
Description
Act_Stat_PM_
Sup
0x3
Slot_Clock_Cfg 1b
Loop back
polarity
0b
inversion
Determines support for Active State Link Power
Management (ASLPM). Loaded into the PCIe Active State
Link PM Support register.
Note: Changing the default value of this field might affect
0x3
certain power savings features of the 82583V. However, in
some applications, it might be necessary to change this
value as explained in the Intel^® 82583V Gigabit Ethernet
Controller Specification Update. Please refer to Erratum #9
for more details.
1b
When set, the 82583V uses the PCIe reference clock
supplied on the connector (for add-in solutions).
Check Polarity Inversion in Loop-Back Master Entry
During normal operation polarity is adjusted during link up.
0b
When this bit is set, the receiver re-checks the polarity of
Rx-data and then inverts it accordingly, when entering a
near-end loopback. When cleared, polarity is not re-
checked after link up.
5.1.1.17 PCIe Control (Word 0x1B)
Bit
15
14
13
12
11
10
9:7
6
5
4
Name
Hardware
Default
NVM
Image
Setting
Description
PCIE_RX_
Valid
0b
Latency_To_E
nter_L1
1b
PCIE Down
Reset Disable
0b
PCIE_LTSSM 0b
Good
Recovery
0b
Leaky Bucket
Disable
1b
Reserved
0x0
Reserved
0b
L2 Disable
0b
Skip Disable 0b
0b
Force receiver presence detection. When set, the 82583V
overrides the receiver (partner) detection status.
MSB [2] of period in L0s state before transitioning into an L1
1b
state (lower bits are in bits [1:0].
Recommended setting: {14, 1:0} = 011b – 32 μs.
0b
Disable a core reset when the PCIe link goes down.
When cleared, LTSSM complies with the SlimPIPE
0b
specification (power mode transition). When set, LTSSM
behaves as in previous generations.
When this bit is set, the LTSSM recovery states always
0b
progress towards link up (force a good recovery when a
recovery occurs).
Disable leaky bucket mechanism in the PCIe PHY. Disabling
1b
this mechanism holds the link from going to recovery retrain
in case of disparity errors.
0x0
Reserved.
0b
Reserved.
0b
Disable the link from entering L2 state.
0b
Disable skip symbol insertion in the elastic buffer.
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