82583V Datasheet, PDF (362/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Diagnostics
13.0 Diagnostics
13.1
13.2
13.3
To assist in test and debug of the software device driver, a set of software-usable
features have been provided in the component. These features include controls for
specific test-mode usage, as well as some registers for verifying the 82583V’s internal
state against what the software device driver is expecting.
Introduction
The 82583V provides software visibility (and controllability) into certain major internal
data structures, including all of the transmit and receive FIFO space. However,
interlocks are not provided for any operations, so diagnostic accesses can only be
performed under very controlled circumstances.
The 82583V also provides software-controllable support for certain loopback modes, to
enable a software device driver to test transmit and receive flows to itself. Loopback
modes can also be used to diagnose communication problems and attempt to isolate
the location of a break in the communications path.
FIFO Pointer Accessibility
The 82583V’s internal pointers into its transmit and receive data FIFOs are visible
through the head and tail diagnostic data FIFO registers. See section 9.2.9. Diagnostics
software can read these FIFO pointers to confirm an expected hardware state following
a sequence of operation(s). Diagnostic software can further write to these pointers as a
partial-step to verify expected FIFO contents following a specific operation, or to
subsequently write data directly to the data FIFOs.
FIFO Data Accessibility
The 82583V’s internal transmit and receive data FIFOs contents are directly readable
and writeable through the PBM register. The specific locations read or written are
determined by the values of the FIFO pointers, which can be read and written. When
accessing the actual FIFO data structures, locations must be accessed as 32-bit words.
See section 9.2.9.
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