82583V Datasheet, PDF (118/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
Note:
TCPE (bit 5) - TCP/UDP checksum error
CXE (bit 4) - Carrier extension error
Rsv (bit 3) - Reserved
SEQ (bit 2) - Sequence error
SE (bit 1) - Symbol error
CE (bit 0) - CRC error or alignment error
The IP and TCP checksum error bits are valid only when the IPv4 or TCP/UDP
checksum(s) is performed on the received packet as indicated via IPCS and TCPCS
previously mentioned. These, along with the other error bits, are valid only when the
EOP and DD bits are set in the descriptor.
Receive checksum errors have no effect on packet filtering.
If receive checksum offloading is disabled (RXCSUM.IPOFL and RXCSUM.TUOFL), the
IPE and TCPE bits are 0b.
The RXE bit indicates that a data error occurred during the packet reception that has
been detected by the PHY. This generally corresponds to signal errors occurring during
the packet reception. This bit is valid only when the EOP and DD bits are set and are
not set in descriptors unless RCTL.SBP (Store-Bad-Packets) is set.
CRC errors and alignment errors are both indicated via the CE bit. Software can
distinguish between these errors by monitoring the respective statistics registers.
7.1.3.5
7.1.4
VLAN Tag Field (16-Bit, Offset 48)
Hardware stores additional information in the receive descriptor for 802.1q packets. If
the packet type is 802.1q (determined when a packet matches VET and RCTL.VME =
1b), then the VLAN Tag field records the VLAN information and the four-byte VLAN
information is stripped from the packet data storage. Otherwise, the VLAN Tag field
contains 0x0000.
15 13
12
11
0
PRI
CFI
VLAN
Extended Rx Descriptor
If the RFCTL.EXSTEN bit is set and RCTL.DTYP equals 00b, the 82583V uses the
extended Rx descriptor as follows:
Descriptor Read Format:
63
0
0
Buffer Address [63:0]
8
Reserved
0
118