82583V Datasheet, PDF (344/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Design Considerations
11.6.1.2
Power Up-Sequence (Internal LVR)
The 82583V controls the power-up sequence internally and automatically with the
following conditions (see Figure 60):
• 3.3 V dc must be the source for the internal LVR.
• 1.9 V dc never exceeds 3.3 V dc.
• 1.05 V dc never exceeds 3.3 V dc or 1.9 V dc.
The ramp
ramp.
is
delayed
internally,
with
T_delay
depending
on
the
rising
slope
of
the
3.3
V
dc
VDD3p3
AVDD1p9
VDD1p0
Figure 60. Internal LVR Power-Up Sequence
11.6.2
Power and Ground Planes
Good grounding requires minimizing inductance levels in the interconnections and
keeping ground returns short, signal loop areas small, and power inputs bypassed to
signal return, will significantly reduce EMI radiation.
The following guidelines help reduce circuit inductance in both backplanes and
motherboards:
• Route traces over a continuous plane with no interruptions. Do not route over a
split power or ground plane. If there are vacant areas on a ground or power plane,
avoid routing signals over the vacant area. This will increase inductance and EMI
radiation levels.
• Separate noisy digital grounds from analog grounds to reduce coupling. Noisy
digital grounds may affect sensitive DC subsystems.
• All ground vias should be connected to every ground plane; and every power via
should be connected to all power planes at equal potential. This helps reduce circuit
inductance.
• Physically locate grounds between a signal path and its return. This will minimize
the loop area.
• Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times
contain many high frequency harmonics, which can radiate EMI.
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