82583V Datasheet, PDF (318/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Programing Interface
10.1.5.2
PCIe Extended Configuration Space
PCIe configuration space is located in a flat memory-mapped address space. PCIe
extends the configuration space beyond the 256 bytes available for PCI to 4096 bytes.
The 82583V decodes additional 4-bits (bits 27:24) to provide the additional
configuration space as shown. PCIe reserves the remaining 4 bits (bits 31:28) for
future expansion of the configuration space beyond 4096 bytes.
The configuration address for a PCIe device is computed using PCI-compatible bus,
device and function numbers as follows:
31
0000b
28
27
Bus #
20
19
Device #
15 14 12 11
2 10
Fun #
Register Address (offset) 00b
PCIe extended configuration space is allocated using a linked list of optional or required
PCIe extended capabilities following a format resembling PCI capability structures. The
first PCIe extended capability is located at offset 0x100 in the device configuration
space. The first Dword of the capability structure identifies the capability/version and
points to the next capability.
The 82583V supports the following PCIe extended capabilities:
• Advanced error reporting capability - offset 0x100
• Device serial number capability - offset 0x140
10.1.5.2.1
Advanced Error Reporting Capability
The PCIe advanced error reporting capability is an optional extended capability to
support advanced error reporting. The following table lists the PCIe advanced error
reporting extended capability structure for PCIe devices.
Register
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C:0x28
Field
Description
PCIe CAP ID
PCIe Extended Capability ID.
Uncorrectable Error Reports error status of individual uncorrectable error sources on a PCIe
Status
device.
Uncorrectable Error Controls reporting of individual uncorrectable errors by device to the
Mask
host bridge via a PCIe error message.
Uncorrectable Error Controls whether an individual uncorrectable error is reported as a fatal
Severity
error.
Correctable Error
Status
Reports error status of individual correctable error sources on a PCIe
device.
Correctable Error
Mask
Controls reporting of individual correctable errors by device to the host
bridge via a PCIe error message.
First Error Pointer
Identifies the bit position of the first uncorrectable error reported in the
Uncorrectable Error Status register.
Header Log
Captures the header for the transaction that generated an error.
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