82583V Datasheet, PDF (242/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
Note:
Note:
There is one register per 32 bits of the multicast address table for a total of 128
registers (thus the MTA[127:0] designation). The size of the word array depends on the
number of bits implemented in the multicast address table. Software must mask to the
desired bit on reads and supply a 32-bit word on writes.
All accesses to this table must be 32-bit.
These registers' addresses have been moved from where they were located in previous
devices. However, for backwards compatibility, these registers can also be accessed at
their alias offsets of 0x00200-0x003FC.
Figure 43 shows the multicast lookup algorithm. The destination address shown
represents the internally stored ordering of the received DA. Note that bit 0 indicated in
this diagram is the first on the wire.
Destination Address
47:40 39:32 31:24 23:16 15:8 7:0
bank[1:0]
word
pointer[11:5]
Multicast Table Array
32 x 128
(4096 bit vector)
?
...
...
bit
pointer[4:0]
Figure 43. Multicast Table Array Algorithm
9.2.5.18
Receive Address Low - RAL (0x05400 + 8*n; RW)
While "n" is the exact unicast/multicast address entry and it is equals to 0,1,…15.
Field
RAL
Bit(s)
31:0
Initial
Value
X
Description
Receive Address Low
The lower 32 bits of the 48-bit Ethernet address.
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