82583V Datasheet, PDF (304/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Programing Interface
Byte Offset
0x28
0x2C
0x30
0x34
0x38
0x3C
Byte 3
Byte 2
Byte 1
Byte 0
Cardbus CIS Pointer (0x00000000)
Subsystem ID (0x0000)
Subsystem Vendor ID (0x8086)
Expansion ROM Base Address
Reserved (0x000000)
Cap_Ptr (0xC8)
Reserved (0x00000000)
Max_Latency (0x00)
Min_Grant
(0x00)
Interrupt Pin
(0x01)
Interrupt Line
(0x00)
Figure 44.
PCI-Compatible Configuration Registers
Explanation of the various registers in the 82583V is as follows.
10.1.2.1
Vendor ID (Offset 0x0)
This is a read-only register that has the same value for all PCI functions. It uniquely
identifies Intel products. The field default value is 0x8086.
10.1.2.2
Device ID (Offset 0x2)
This is a read-only register. The value is loaded from NVM. Default value is 0x150C for
the 82583V.
10.1.2.3
PCI
Function
LAN
Default
Value
0x150C
NVM Address
Meaning
0x0D
10/100/1000 Mb/s Ethernet controller, x1
PCIe, copper
Command Reg (Offset 0x4)
Read-write register. Layout is as follows. Shaded bits are not used by this
implementation and are hardwired to 0b.
Bit(s)
0
1
2
3
4
5
6
7
8
9
10
15:11
Init Value
Description
0b
I/O Access Enable.
0b
Memory Access Enable.
0b
Enable Mastering LAN R/W field.
0b
Special Cycle Monitoring – Hardwired to 0b.
0b
MWI Enable – Hardwired to 0b.
0b
Palette Snoop Enable – Hardwired to 0b.
0b
Parity Error Response.
0b
Wait Cycle Enable – Hardwired to 0b.
0b
SERR# Enable.
0b
Fast Back-to-Back Enable – Hardwired to 0b.
Interrupt Disable
0b
Controls the ability of a PCIe device to generate a legacy interrupt
mmeessssaaggees. _.When set, the device can’t generate legacy interrupt
0b
Reserved
304