82583V Datasheet, PDF (227/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.4.3
Interrupt Cause Set Register - ICS (0x000C8; W)
Field
TXDW
TXQE
LSC
Reserved
RXDMT0
Reserved
RXO
RXT0
reserved
MDAC
Reserved
Reserved
Reserved
Reserved
TXD_LOW
SRPD
ACK
Reserved
RxQ0
Reserved
TxQ0
Reserved
Other
Reserved
Bit(s)
0
1
2
3
4
5
6
7
8
9
10
11
12
14:13
15
16
17
19:18
20
21
22
23
24
31:25
Initial
Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
X
Description
Sets Transmit Descriptor Written Back
Sets Transmit Queue Empty
Sets Link Status Change.
Reserved
Sets Receive Descriptor Minimum Threshold Hit
Reserved
Sets Receiver Overrun
Set on receive data FIFO overrun.
Sets Receiver Timer Interrupt
Reserved
Sets MDIO Access Complete Interrupt
Reserved
Reserved
Reserved
Reserved
Transmit Descriptor Low Threshold Hit
Small Receive Packet Detected and Transferred
Sets Receive ACK Frame Detected
Reserved
Sets Receive Queue 0 Interrupt
Reserved
Sets Transmit Queue 0 Interrupt
Reserved
Sets Other Interrupt
Reserved
Should be written with 0x0 to ensure future compatibility
Software uses this register to set an interrupt condition. Any bit written with a 1b sets
the corresponding interrupt. This results in the corresponding bit being set in the
Interrupt Cause Read register (see Section 9.2.4.1). A PCIe interrupt is also generated
if one of the bits in this register is set and the corresponding interrupt is enabled via
the Interrupt Mask Set/Read register (see Section 9.2.4.4).
Bits written with 0b are unchanged.
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