82583V Datasheet, PDF (339/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Design Considerations—82583V GbE Controller
11.5.5.5
11.5.5.6
Note:
11.5.5.7
11.5.5.8
Signal Termination and Coupling
The 82547L has internal termination on the MDI signals. External resistors are not
needed. Adding pads for external resistors can degrade signal integrity.
Signal Trace Geometry for 1000 BASE-T Designs
The key factors in controlling trace EMI radiation are the trace length and the ratio of
trace-width to trace-height above the reference plane. To minimize trace inductance,
high-speed signals and signal layers that are close to a reference or power plane should
be as short and wide as practical. Ideally, this trace width to height above the ground
plane ratio is between 1:1 and 3:1. To maintain trace impedance, the width of the trace
should be modified when changing from one board layer to another if the two layers are
not equidistant from the neighboring planes.
Each pair of signal should have a differential impedance of 100 Ω. +/- 15%. If a
particular tool cannot design differential traces, it is permissible to specify 55-65 Ω
single-ended traces as long as the spacing between the two traces is minimized. As an
example, consider a differential trace pair on Layer 1 that is 8 mils (0.2 mm) wide and
2 mils (0.05 mm) thick, with a spacing of 8 mils (0.2 mm). If the fiberglass layer is 8
immilpse(d0a.n2cme wmo)utlhdicbkewaipthpraoxdiimelaetcetlryic6c1onΩ^{staanndt,thEeR,coaflc4u.l7a,tetdhedicfafelcruenlattieadl} imsinpgeldea-nenceded
would be approximately 100 Ω.
When performing a board layout, do not allow the CAD tool auto-router to route the
differential pairs without intervention. In most cases, the differential pairs will have to
be routed manually.
Measuring trace impedance for layout designs targeting 100 Ω often results in lower
actual impedance. Designers should verify actual trace impedance and adjust the
layout accordingly. If the actual impedance is consistently low, a target of 105 – 110 Ω
should compensate for second order effects.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the
differential impedance by up to 10 Ω, when the traces within a pair are closer than 30
mils (edge to edge).
Trace Length and Symmetry for 1000 BASE-T Designs
As indicated earlier, the overall length of differential pairs should be less than four
inches measured from the Ethernet device to the magnetics.
The differential traces (within each pair) should be equal in total length to within 50
mils (1.25 mm) and as symmetrical as possible. Asymmetrical and unequal length
traces in the differential pairs contribute to common mode noise. If a choice has to be
made between matching lengths and fixing symmetry, more emphasis should be placed
on fixing symmetry. Common mode noise can degrade the receive circuit’s performance
and contribute to radiated emissions.
Routing 1.9 V dc to the Magnetics Center Tap
The central-tap 1.9 V dc should be delivered as a solid supply plane (1.9 V dc) directly
to the magnetic module or, if this is not possible, by a short and thick trace (lower than
0.2 Ω DC resistance). The decoupling capacitors for the central tap pins should be
placed as close as possible to the magnetic component. This improves both EMI and
IEEE compliance.
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