82583V Datasheet, PDF (200/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.2.2
Device Status Register - STATUS (0x00008; R)
Field
Bit(s)
FD
0
LU
1
Reserved
3:2
TXOFF
4
Reserved
5
SPEED
7:6
ASDV
9:8
PHYRA
10
Reserved
18:11
GIO Master
Enable Status
19
Reserved
Reserved
30:20
31
Initial
Value
X
X
00b
X
0b
X
X
1b
0x0
1b
0x0
0b
Description
Full Duplex
0b = half duplex
1b = Full duplex. Reflects duplex setting of the MAC and/or link.
Link Up
0b = No link established
1b = Link established. For this to be valid, the Set Link Up bit of the
Device Control (CTRL.SU) register must be set.
Reserved
Transmission Paused
Indication of pause state of the transmit function when symmetrical
flow control is enabled.
Reserved
Link speed setting. Reflects speed setting of the MAC and/or link
00b = 10 Mb/s
01b = 100 Mb/s
10b = 1000 Mb/s
11b = 1000 Mb/s
Auto-Speed Detection Value
Speed result sensed by the MAC auto-detection function.
PHY Reset Asserted
This bit is read/write. Hardware sets this bit following the assertion of
PHY reset. The bit is cleared on writing 0b to it. This bit is used by
firmware as an indication for required initialization of the PHY.
Reserved
Cleared by the 82583V when the GIO Master Disable bit is set and no
master requests are pending by this function. Set otherwise.
Indicates that no master requests is issued by this function as long as
the GIO Master Disable bit is set.
Reserved
Reads as 0b.
Reserved
FD reflects the actual MAC duplex configuration. This normally reflects the duplex
setting for the entire link, as it normally reflects the duplex configuration negotiated
between the PHY and link partner (copper link) or MAC and link partner (fiber link).
Link up provides a useful indication of whether something is attached to the port.
Successful negotiation of features/link parameters results in link activity. The link start-
up process (and consequently the duration for this activity after reset) can be several
100's of μs. It reflects whether the PHY's LINK indication is present. Refer to
Section 6.2.3 for more details.
TXOFF indicates the state of the transmit function when symmetrical flow control has
been enabled and negotiated with the link partner. This bit is set to 1b when
transmission is paused due to the reception of an XOFF frame. It is cleared upon
expiration of the pause timer or the receipt of an XON frame.
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