82583V Datasheet, PDF (365/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Board Layout and Schematic Checklists—82583V GbE Controller
Section
Check Item
Remarks
Clock Source
(Oscillator
Option)
EEPROM or
Flash
Memory
10/100/
1000Base-T
Interface
Traces
Ensure the oscillator has a it's own local
power supply decoupling capacitor.
If the oscillator is shared or is more than
two inches away from the 82583V, a back-
termination resistor should be placed near
the oscillator for each 82583V.
This enables tuning to ensure that reflections do not distort the
clock waveform.
Keep clock lines away from other digital
traces (especially reset signals), I/O ports,
board edge, transformers and differential
pairs.
This reduces EMI.
The NVM can be placed a few inches away
from the 82583V to provide better spacing
of critical components.
Design traces for 100 Ω differential
impedance (± 20%).
Primary requirement for 10/100/1000 Mb/s Ethernet. Paired
50 Ω traces do not make 100 Ω differential. An impedance
calculator can be used to verify this.
Avoid highly resistive traces (for example,
avoid four mil traces longer than four
inches).
If trace length is a problem, use thicker board dielectrics to
allow wider traces. Thicker copper is even better than wider
traces.
If a LAN switch is used or the trace length
from the 82583V is greater than four
inches. It might be necessary to boost the
voltage at the center tap with a separate
power supply to optimize MDI
performance.
Consider using a second 82583V instead of a LAN switch and
long MDI traces. It is difficult to achieve excellent performance
with long traces and analog LAN switches. Additional
optimization effort is required to tune the system, the center
tap voltage, and magnetics modules.
Make traces symmetrical.
Pairs should be matched at pads, vias and turns. Asymmetry
contributes to impedance mismatch.
Do not make 90° bends.
Bevel corners with turns based on 45° angles
Avoid through holes (vias).
If vias are used, the budget is two per trace.
Keep traces close together inside a
differential pair.
Traces should be kept within 10 mils regardless of trace
geometry.
Keep trace-to-trace length difference
within each pair to less than 50 mils.
This minimizes signal skew and common mode noise.
Improves long cable performance.
Pair-to-pair trace length does not have to
be matched as differences are not critical.
The difference between the length of longest pair and the
length of the shortest pair should be kept below two inches.
Keep differential pairs more than seven
times the dielectric thickness away from
each other and other traces, including
NVM traces and parallel digital traces.
This minimizes crosstalk and noise injection. Tighter spacing is
allowed for the first 200 mils of trace near of the components.
Ensure that line side MDI traces and line
side termination are at least 80 mils from
all other traces.
This is to ensure the system can survive a high voltage on the
MDI cable. (Hi-POT)
Keep traces at least 0.1 inches away from
the board edge.
This reduces EMI.
Do not have stubs along the traces.
Stubs cause discontinuities that impact return loss.
Digital signals on adjacent layers must
cross at 90° angles. Splits in power and
ground planes must not cross.
Differential pairs should be run on different layers as needed to
improve routing.
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