82583V Datasheet, PDF (82/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.1.1.1
6.1.1.2
6.1.2
6.1.3
6.1.3.1
Table 25.
Physical Interface Properties
• Point to point interconnect
— Full-duplex; no arbitration
• Signaling technology:
— Low voltage differential
— Embedded clock signaling using 8b/10b encoding scheme
• Serial frequency of operation: 2.5 GHz.
• Interface width of one lane per direction
• DFT and DFM support for high volume manufacturing
Advanced Extensions
PCIe defines a set of optional features to enhance platform capabilities for specific
usage modes. The 82583V supports the following optional features:
• Extended error reporting – messaging support to communicate multiple types/
severity of errors
• Serial number
General Functionality
• Native/legacy:
— The PCIe capability register states the device/port type.
— The 82583V is a native device by default.
• Locked transactions:
— The 82583V does not support locked requests as a target or master.
• End to End CRC (ECRC):
— Not supported by the 82583V
Transaction Layer
The upper layer of the PCIe architecture is the transaction layer. The transaction layer
connects to the 82583V’s core using an implementation-specific protocol. Through this
core-to-transaction-layer protocol, the application-specific parts of the 82583V interact
with the PCIe subsystem and transmit and receive requests to or from the remote PCIe
agent, respectively.
Transaction Types Received by the Transaction Layer
Transaction Types at the Rx Transaction Layer
Transaction Type
Configuration Read
Request
Configuration Write
Request
Memory Read
Request
FC Type
NPH
NPH +
NPD
NPH
Tx Later
Reaction
Hardware Should Keep
Data From Original Packet
For Client
CPLH + CPLD Requester ID, TAG, Attribute Configuration space
CPLH
Requester ID, TAG, Attribute Configuration space
CPLH + CPLD Requester ID, TAG, Attribute CSR
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