82583V Datasheet, PDF (261/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.7.31 Good Octets Transmitted Count - GOTCL (0x04090; R)
9.2.7.32 Good Octets Transmitted Count - GOTCH (0x04094; R)
9.2.7.33
Field
GOTCL
GOTCH
Bit(s)
31:0
31:0
Initial
Value
0x0
0x0
Description
Number of good octets transmitted – lower 4 bytes.
Number of good octets transmitted – upper 4 bytes.
These registers make up a logical 64-bit register that counts the number of good (non-
erred) octets transmitted. This register must be accessed using two independent 32-bit
accesses. This register resets whenever the upper 32 bits are read (GOTCH).
In addition, it sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached.
This register includes bytes transmitted in a packet from the <Destination Address>
field through the <CRC> field, inclusively. This register counts octets in successfully
transmitted packets which are 64 or more bytes in length. This register only increments
if transmits are enabled. The register counts clear as well as secure octets.
These octets do not include octets in transmitted flow control packets.
Receive No Buffers Count - RNBC (0x040A0; R)
9.2.7.34
Field
RNBC
Bit(s)
31:0
Initial
Value
0x0
Description
Number of receive no buffer conditions.
This register counts the number of times that frames were received when there were
no available buffers in host memory to store those frames (receive descriptor head and
tail pointers were equal). The packet is still received if there is space in the FIFO. This
register only increments if receives are enabled.
This register does not increment when flow control packets are received.
Receive Undersize Count - RUC (0x040A4; R)
Field
RUC
Bit(s)
31:0
Initial
Value
0x0
Description
Number of receive undersize errors.
This register counts the number of received frames that passed address filtering, and
were less than minimum size (64 bytes from <Destination Address> through <CRC>,
inclusively), and had a valid CRC. This register only increments if receives are enabled.
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