82583V Datasheet, PDF (179/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Power Management and Delivery—82583V GbE Controller
PCIe Reference
Clock
PCIe PwrGd
Internal PCIe clock
(2.5 GHz)
Internal PwrGd
(PLL)
Reading EEPROM
4a
tclkp
g
3
tl2pg
4b
tl2clk
tpgdl
5
tPWRGD-CLK
6
tppg-
clkint₇
tclkp
8_r
9
tee
Auto
Ext.
Read ₁₁ Conf.
Reset to PHY
(active low) _{D3 write}
2
1
PCIe Link L0
L1
L0
L2/L3
tpgtrn
12
tpgcfg
13
tpgres
14
15
L0
10
Wake Up Enabled
Any mode
APM
PHY Power State full
power-managed
DState D0a
D3
Dr
D0u
full
D0a
Figure 42.
Table 47.
D3cold Transition Timing Diagram
Notes to D3cold Timing Diagram
Note
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Description
Writing 11b to the Power State field of the PMCSR transitions the 82583V to D3. PCIe link transitions
to L1 state.
The system can delay an arbitrary amount of time between setting D3 mode and transition the link to
an L2 or L3 state.
Following link transition, PE_RST_N is asserted.
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait tl2clk
after link transition to L2/L3 before stopping the reference clock.
On assertion of PE_RST_N, the 82583V transitions to Dr state.
The system starts the PCIe reference clock t_PWRGD-CLK before de-asserting PE_RST_N.
The Internal PCIe clock is valid and stable t_ppg-clkint from PE_RST_N de-assertion.
The PCIe Internal PWRGD signal is asserted tclkpr after the external PE_RST_N signal.
Asserting Internal PCIe PWRGD causes the NVM to be re-read, asserts PHY reset, and disables wake
up.
APM wake-up mode can be enabled based on what is read from the NVM.
After reading the NVM, PHY reset is de-asserted.
Link training starts after tpgtrn from PE_RST_N de-assertion.
A first PCIe configuration access might arrive after t_pgcfg from PE_RST_N de-assertion.
A first PCI configuration response can be sent after tpgres from PE_RST_N de-assertion
Writing a 1b to the Memory Access Enable bit in the PCI Command register transitions the device
from the D0u to D0 state.
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