82583V Datasheet, PDF (228/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.4.4
Interrupt Mask Set/Read Register - IMS (0x000D0; RW)
Field
TXDW
TXQE
LSC
Reserved
RXDMT0
Reserved
RXO
RXT0
reserved
MDAC
Reserved
Reserved
Reserved
Reserved
TXD_LOW
SRPD
ACK
Reserved
RxQ0
Reserved
TxQ0
Reserved
Other
Reserved
Bit(s)
0
1
2
3
4
5
6
7
8
9
10
11
12
14:13
15
16
17
19:18
20
21
22
23
24
31:25
Initial
Value
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0x0
0b
0b
0b
X
0b
0b
0b
0b
0b
x0
Description
Sets the mask for transmit descriptor written back.
Sets the mask for transmit queue empty.
Sets the mask for link status change.
Reserved
Sets the mask for receive descriptor minimum threshold hit.
Reserved.
Sets mask for receiver overrun. Set on receive data FIFO overrun.
Sets mask for receiver timer interrupt.
Reserved
Sets mask for MDIO access complete interrupt.
Reserved
Reserved
Reserved
Reserved
Sets the mask for transmit descriptor low threshold hit.
Sets the mask for small receive packet detection.
Sets the mask forreceive ACK frame detection.
Reserved
Sets the mask for receive queue 0 interrupt.
Reserved
Sets the mask for transmit queue 0 interrupt.
Reserved
Sets the mask for other interrupt.
Reserved
Should be written with 0x0 to ensure future compatibility.
Reading this register returns which bits have an interrupt mask set. An interrupt is
enabled if its corresponding mask bit is set to 1b, and disabled if its corresponding
mask bit is set to 0b. A PCIe interrupt is generated whenever one of the bits in this
register is set, and the corresponding interrupt condition occurs. The occurrence of an
interrupt condition is reflected by having a bit set in the Interrupt Cause Read register
(see Section 9.2.4.1).
A particular interrupt can be enabled by writing a 1b to the corresponding mask bit in
this register. Any bits written with a 0b, are unchanged. Thus, if software desires to
disable a particular interrupt condition that had been previously enabled, it must write
to the Interrupt Mask Clear register (see Section 9.2.4.5), rather than writing a 0b to a
bit in this register.
When the CTRL_EXT.INT_TIMERS_CLEAR_ENA bit is set, then following writing all 1b's
to the IMS register (enable all interrupts) all interrupt timers are cleared to their initial
value. This auto clear provides the required latency before the next INT event.
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