82583V Datasheet, PDF (212/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.2.15
Notes:
1. When LED blink mode is enabled the appropriate LED Invert bit should be set to
zero.
2. The dynamic Leds modes (FILTER_ACTIVITY, LINK/ACTIVITY, COLLISION,
ACTIVITY, PAUSED) should be used with LED blink mode enabled.
3. When LED blink mode is enabled and CCM PLL is shut, the blinking frequencies are
1/5 of the rates stated in the previous table.
Extended Configuration Control - EXTCNF_CTRL (0x00F00; RW)
Field
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit(s)
31:28
27:16
15:8
7
6
5
4
3
2
1
0
Initial
Value
0b
0x0
0x0
0b
0b
0b
0b
1b
0b
0b
0b
Description
Reserved
Reserved
Reserved
MDIO MNG Ownership: Management request for access to MDIO. This
is part of the semaphore scheme for MDIO access (Section 4.6.2).
This is a RO bit.
Note: Use of this register is optional for the 82583V.
MDIO/NVM HW Ownership: Hardware request fo raccess to MDIO/
EEPROM. This is part of the semaphore scheme for MDIO access
(Section 4.6.2). This is a RO bit.
Note: Use of this register is optional for the 82583V.
MDIO/NVM SW Ownership: Software request fo raccess to MDIO/
EEPROM. This is part of the semaphore scheme for MDIO access
(Section 4.6.2). This is a RO bit.
Note: Use of this register is optional for the 82583V.
Reserved
Reserved
Reserved
Reserved
Should be set to 0b.
9.2.2.16 Extended Configuration Size - EXTCNF_SIZE (0x00F08; RW)
Field
Reserved
Reserved
Bit(s)
31:8
7:0
Initial
Value
0x0
0x0
Reserved
Reserved
Description
212