82583V Datasheet, PDF (97/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.2.2.1
6.2.2.2
Note:
6.2.3
Full Duplex
All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are
supported in full duplex operation. Full duplex operation is enabled by several
mechanisms, depending on the speed configuration of the 82583V and the specific
capabilities of the link partner used in the application. During full duplex operation, the
82583V might transmit and receive packets simultaneously across the link interface.
In full-duplex GMII/MII mode, transmission and reception are delineated independently
by the GMII/MII control signals. Transmission starts at the assertion of TX_EN, which
indicates there is valid data on the TX_DATA bus driven from the MAC to the PHY.
Reception is signaled by the PHY by the assertion of the RX_DV signal, which indicates
valid receive data on the RX_DATA lines to the MAC.
Half Duplex
The 82583V MAC can operate in half duplex.
In half duplex operation, the MAC attempts to avoid contention with other traffic on the
link by monitoring the CRS signal provided by the PHY and deferring to passing traffic.
When the CRS signal is de-asserted or after a sufficient Inter-Packet Gap (IPG) has
elapsed after a transmission, frame transmission begins. The MAC signals the PHY with
TX_EN at the start of transmission.
If a collision occurs, the PHY detects the collision and asserts the COL signal to the
MAC. Transmitting the frame stops within four link clock times and the 82583V sends a
JAM sequence onto the link. After the end of a collided transmission, the 82583V backs
off and attempts to re-transmit per the standard CSMA/CD method.
The re-transmissions are done from the data stored internally in the 82583V MAC
transmit packet buffer (no re-access to the data in host memory is performed).
After a successful transmission, the 82583V is ready to transmit any other frame(s)
queued in the MAC's transmit FIFO, after the minimum Inter-Frame Spacing (IFS) of
the link has elapsed.
During transmit, the PHY is expected to signal a carrier-sense (assert the CRS signal)
back to the MAC before one slot time has elapsed. The transmission completes
successfully even if the PHY fails to indicate CRS within the slot time window; if this
situation occurs, the PHY can either be configured incorrectly or be in a link down
situation. Such an event is counted in the Transmit Without CRS statistic register (see
section 9.2.7.11).
Auto-Negotiation & Link Setup Features
The method for configuring the link between two link partners is highly dependent on
the mode of operation.
Configuration of the link can be accomplished by several methods ranging from:
• software's forcing link settings
• software-controlled negotiation
• MAC-controlled auto-negotiation
• auto-negotiation initiated by a PHY.
The following sections describe processes of bringing the link up including configuration
of the 82583V and the transceiver, as well as the various methods of determining
duplex and speed configuration.
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