82583V Datasheet, PDF (176/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Power Management and Delivery
8.4.4.3
Note:
8.4.4.3.1
Dr State
Transition to Dr state is initiated on three occasions:
• At system power up - Dr state begins with the assertion of the internal power
detection circuit (Internal Power On Reset) and ends with the assertion of the
Internal Pwrgd signal (indicating that the system de-asserted its PCIe PE_RST_N
signal).
• At transition from a D0a state - During operation, the system might assert PCIe
PE_RST_N at any time. In an ACPI system, a system transition to the G2/S5 state
causes a transition from D0a to Dr state.
• At transition from a D3 state - The system transitions the device into the Dr state
by asserting PCIe PE_RST_N.
The 82583V meets the restrictions on using auxiliary power, defined in the PCI-PM
specification:
1. If wake is enabled (either APM wake or ACPI wake), then the 82583V might
consume up to 375 mA @ 3.3 V dc.
2. If wake is disabled, then the 82583V might consume up to 20 mA @ 3.3 V dc.
The restrictions apply to all cases of Dr state (power up, D3 entry, Dr entry from D0).
When the wake configuration is unknown (for example, during power up before an NVM
read), the 82583V must meet the 20 mA limit.
The system might maintain PE_RST_N asserted for an arbitrary time. The de-assertion
(rising edge) of PE_RST_N causes a transition to D0u state.
Any Wake-up filter settings that were enabled before entering this reset state are
maintained.
Entry to Dr State
Dr entry on platform power up begins by asserting the internal power detection circuit
(Internal Power On Reset). The NVM is read and determines device configuration. If the
APM Enable bit in the NVM's Initialization Control Word 2 is set, then APM wake up is
enabled. The PHY and MAC states are determined by the state of APM wake. To reduce
power consumption, if APM wake is enabled, the PHY auto-negotiates to a lower link
speed on Dr entry (see Section 8.4.4.3.1). The PCIe link is not enabled in Dr state
following system power up (since PERS# is asserted).
Entry to Dr state from D0a state is by asserting the PE_RST_N signal. An ACPI
transition to the G2/S5 state is reflected in a device transition from D0a to Dr state.
The transition might be orderly (for example, the designer selected the shut down
option), in which case the software device driver might have a chance to intervene. Or,
it might be an emergency transition (such as, power button override), in which case,
the software device driver is not notified.
To reduce power consumption, if APM wake or PCI-PM PME is enabled, the PHY auto-
negotiates to a lower link speed on D0a to Dr transition (see Section 8.4.4.3.1).
Transition from D3 state to Dr state is done by asserting the PE_RST_N signal. Prior to
that, the system initiates a transition of the PCIe link from the L1 state to either the L2
or L3 state. The link enters L2 state if PCI-PM PME is enabled.
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