82583V Datasheet, PDF (324/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Design Considerations
11.0 Design Considerations
11.1
11.1.1
11.1.2
11.1.3
This section provides general design considerations and recommendations when
selecting components and connecting special pins to the 82583V.
PCIe
Port Connection to the 82583V
PCIe is a dual simplex point-to-point serial differential low-voltage interconnect with a
signaling bit rate of 2.5 Gb/s per direction. The 82583V’s PCIe port consists of an
integral group of transmitters and receivers. The link between the PCIe ports of two
devices is a x1 lane that also consists of a transmitter and a receiver pair. Note that
each signal is 8b/10b encoded with an embedded clock.
The PCIe topology consists of a transmitter (Tx) located on one device connected
through a differential pair connected to the receiver (Rx) on a second device. The
82583V can be located on a motherboard or on an add-in card using a connector
specified by PCIe.
The lane is AC-coupled between its corresponding transmitter and receiver. The AC-
coupling capacitor is located on the board close to transmitter side. Each end of the link
is terminated on the die into nominal 100 Ω differential DC impedance. Board
termination is not required.
For more information on PCIe, refer to the PCI Express* Base Specification, Revision
1.1 and PCI Express* Card Electromechanical Specification, Revision 1.1RD.
For information about the 82583V’s PCIe power management capabilities, see
section 8.0.
PCIe Reference Clock
The 82583V uses a 100 MHz differential reference clock, denoted PECLKp and PECLKn.
This signal is typically generated on the system board and routed to the PCIe port. For
add-in cards, the clock is furnished at the PCIe connector.
The frequency tolerance for the PCIe reference clock is +/- 300 ppm.
Other PCIe Signals
The 82583V also implements other signals required by the PCIe specification. The
82583V signals power management events to the system using the PE_WAKE_N signal,
which operates very similarly to the familiar PCI PME# signal. Finally, there is a
PE_RST_N signal, which serves as the familiar reset function for the 82583V.
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