82583V Datasheet, PDF (36/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Initialization
4.0
4.1
4.2
Initialization
Introduction
This chapter discusses initialization steps. This includes:
• General hardware power-up state
• Basic device configuration
• Initialization of transmit and receive operation
• Link configuration and software reset capability
• Statistics initialization
Reset Operation
The 82583V reset sources are as follows:
• Internal Power On Reset- The 82583V has an internal mechanism for sensing the
power pins. Once power is up and stable, the 82583V implements an internal reset.
This reset acts as a master reset of the entire chip. It is level sensitive, and while it
is 0b holds all of the registers in reset. Internal Power On Reset is an indication that
device power supplies are all stable. Internal Power On Reset changes state during
system power up.
• PE_RST_N - Indicates that both the power and the PCIe clock sources are stable; a
value of 0b indicates reset active. This pin asserts an internal reset also after a
D3cold exit. Most units are reset on the rising edge of PE_RST_N. The only
exception is the PCIe unit, which is kept in reset while PE_RST_N is active.
• Device Disable/Dr Disable - The 82583V enters a device disable mode when the
DEV_OFF_N pin is asserted without shutdown (see Section 8.4.4.4). The 82583V
enters Dr disable mode when certain conditions are met in the Dr state (see
Section 8.4.4.3).
• In-band PCIe reset - The 82583V generates an internal reset in response to a
Physical Layer (PHY) message from PCIe or when the PCIe link goes down (entry to
polling or detect state). This reset is equivalent to PCI reset in previous (PCI) GbE
controllers.
• D3hotD0 transition - This is also known as ACPI reset. The 82583V generates an
internal reset on the transition from D3hot power state to D0 (caused after
configuration writes from D3 to D0 power state). Note that this reset is per function
and resets only the function that transitioned from D3hot to D0.
• Software Reset - Software can reset the 82583V by writing the Device Reset bit of
the Device Control (CTRL.RST) register. The 82583V re-reads the per-function NVM
fields after a software reset. Bits that are normally read from the NVM are reset to
their default hardware values. Note that this reset is per function and resets only
the function that received the software reset. PCI configuration space
(configuration and mapping) of the device is unaffected.
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